EDA Design Flow Development Engineer

Intel Corporation; Folsom (CA); Hybrid; USD 142,000 - 269,000; Full time

Job summary

Intel Corporation in California seeks an experienced EDA CAD / Tool Flow Development Engineer to develop transistor-level EM/IR analysis flows for advanced nodes across IPs and macros. You will work with circuit; physical; reliability; and signoff teams to enable scalable EM/IR methodologies and silicon correlation.

The role emphasizes CAD methodology, automation infrastructure, and power integrity analysis, with a hybrid work model and locations in Santa Clara, Folsom, Hillsboro, Austin, and

Qualifications

• Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science; 6+ years experience; or 4+ years with a Master's; or 2+ years with a PhD.
• EM/IR reliability concepts (Electromigration, and Power Drop)
• Experience with CMOS circuit operation, Power delivery networks, SPICE simulation, Parasitic extraction fundamentals, Advanced-node design challenges, Transistor-level power integrity analysis flows, Scripting and automation in Linux environments.

Skills

EM/IR concepts

SPICE

Scripting & Linux automation

Education

Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science

Master's degree

PhD

Tools

Redhawk/Totem

Job description

Job Details: Job Description: The Role and Impact Join Intel in shaping the future of technology. As an EDA Tools Hardware Engineer, you will play a pivotal role in enabling groundbreaking innovations that power Intel's leadership in semiconductor design and manufacturing. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level electromigration (EM) and IR drop analysis flows for custom IPs, embedded memories, SRAMs, analog/mixed-signal interfaces, and high-performance custom macros across advanced semiconductor technologies. This role focuses on CAD methodology, automation infrastructure, power integrity analysis flows, and silicon correlation for transistor-level reliability verification. The engineer will work closely with circuit design, physical design, package, reliability, and signoff teams to enable scalable and accurate EM/IR analysis methodologies for advanced-node designs. The ideal candidate has strong expertise in transistor-level power integrity analysis, SPICE-based verification, parasitic-aware reliability modeling, and automation development using industry-standard EM/IR signoff tools.

Qualifications

Minimum Qualifications Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field, and 6+ years of experience; 4+ years of experience with a Master's degree; or 2+ years of experience with a PhD. EM/IR reliability concepts (Electromigration, and Power Drop) Experience with Redhawk/Totem tools Preferred Qualifications Experience in the following: CMOS circuit operation Power delivery networks SPICE simulation Parasitic extraction fundamentals Advanced-node design challenges Transistor-level power integrity analysis flows Scripting and automation skills in Linux environments

Job Information

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations: US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin

Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

• Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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