ECC Design Engineering Intern

SK hynix memory solutions; San Jose (CA); On-site; USD 48,000 - 62,000; Full time

Job summary

SK Hynix Memory Solution seeks a motivated intern to contribute to Start-of-Art ECC IPs in the ESSD area. The role focuses on FPGA system work, data collection, and RTL coding in Verilog/SystemVerilog under supervision. It requires strong lab skills and reliable communication with design and verification teams.

The internship is 6 months, onsite at San Jose, with a 40-hour workweek. Start date is immediate (Sept/Oct 2026). Compensation ranges from $35 to $45 per hour.

Qualifications

• Proficiency in Verilog/SystemVerilog programming languages.
• Lab skills on Windows software/hardware and FPGA systems.
• Must be available to work 40 hours per week, Monday–Friday.

Responsibilities

• Work on running FPGA systems and collect data for performance.
• Code RTL logic with Verilog syntax.
• Run simulations using Synopsys VCS.
• Debug simulation environments and resolve compilation/simulation issues.
• Collaborate with designers and verification engineers to find correct solutions.

Skills

Verilog

SystemVerilog

Education

EE/CE degree

Tools

Synopsys VCS

Job description

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Internship Duration: 6 months

Hours: 40 hours per week

Start Date: Immediately (September 2026 /October 2026)

Location: San Jose

About The Role

We are seeking a highly motivated and detail-oriented intern to join our team to contribute to SK Start-of-Art ECC (Error Correction Coding) IPs, which is the most critical part in ESSD.

Responsibilities

• Perform work on running FPGA System and collecting data for performance
• Should be able to code RTL logic with Verilog syntax.
• Should be able to run simulation using Synopsys VCS.
• Should be able to debug simulation environment; compilation failure, simulation hang, simulation functional failure, etc.
• Should be able to communicate with designers, verification engineers, and other team for the correct solution.

Minimum Qualifications

• Lab skill on windows software and hardware, and FPGA system.
• BS/MS degree (completed or in progress) in Electrical Engineering, Computer Engineering, or a related field.
• Must have proficiency in Verilog, SystemVerilog programming language.
• Must have good communication within co-working environments.
• Must have good work ethic, i.e. punctual on deadline, trustworthy commitment on assignment.
• Must be available to work 40 hours per week, Monday – Friday.
• 100% onsite commitment for a 6-month duration.

Preferred Qualifications

• Have a mindset on problem solving.
• Understand ASIC/FPGA workflow from concept to real silicon
• Scripting language skills such as Python, Perl, Tcl, etc.
• Experience in LDPC or Algebra code (BCH/RS) is a plus

COMPENSATION: $35/hr - $45/hr

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