DRAM Process Integration Engineer

Micron Technology, Inc; Boise (ID); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Income protection programs

Paid family leave

Paid time-off

Paid holidays

Job summary

Micron Technology, Inc in Boise, Idaho, is seeking a DRAM Process Integration Engineer to lead technology integration activities and ensure the manufacturability of state-of-the-art DRAM technology. The position requires engagement with cross-functional teams and a strong background in semiconductor device physics.

The ideal candidate will possess detailed knowledge of memory technologies, a Master’s degree in Engineering, and 7-10+ years of relevant experience. The role includes a comprehensive benefits package, including medical and paid family leave.

Qualifications

• 7–10+ years of semiconductor industry experience required.
• Experience with process development and integration issues.
• Knowledge of data analysis, DOE, and statistical techniques needed.

Responsibilities

• Lead technology integration activities for DRAM manufacturing.
• Engage with cross-functional teams to solve yield and margin issues.
• Design and conduct experiments in the R&D fab.
• Summarize and address complex yield issues.

Skills

Memory technologies knowledge (DRAM, NAND)

Expertise in semiconductor device physics

Understanding of semiconductor process integration

Data analysis proficiency

Education

MS in Engineering

PhD in Engineering (preferred)

Job description

DRAM Process Integration Engineer

As a process integration engineer in the DRAM organization, you will be part of a team of world‑class engineers working in a leading 300mm R&D facility. Your focus will be the performance and manufacturability of Micron’s next‑generation memories, particularly integration and circuit issues specific to DRAM technology.

Responsibilities

• Lead technology integration activities to enable manufacturability of state‑of‑the‑art DRAM technology.
• Engage with cross‑functional teams—process development, product engineering, design, yield improvement, advanced mask, and probe—to arrive at solutions to yield and margin issues.
• Design and conduct experiments in the R&D fab.
• Optimize process flows and develop creative solutions to meet product requirements.
• Extract, supervise, analyze, and react to inline data, defect data, param data, and probe data to fix yield issues, enhance performance, improve reliability, add process margin, and reduce costs.
• Lead or participate in continuous yield improvement and cost‑reduction activities.
• Summarize sophisticated problems, derive and explain actions taken to address them, and drive the team to implement them.

Minimum Qualifications

• Detailed knowledge of mainstream memory technologies such as DRAM and NAND acquired through significant proven contributions.
• Expert in semiconductor device physics.
• Strong understanding of semiconductor process integration and process development.
• Familiarity with both process integration and circuit/architecture issues as they relate to memory.
• MS in an engineering field paired with 7–10+ years of relevant semiconductor industry experience.

Preferred Qualifications

• PhD in an engineering field paired with 5+ years of relevant semiconductor industry experience.
• Proven project management skills and experience driving multi‑functional technical teams.
• Proficiency with data analysis, DOE, and statistical techniques.
• Understanding of the challenges and opportunities facing alternative memory technologies.

Benefits

Micron offers a comprehensive benefits package that includes medical, dental, and vision plans, income protection programs, paid family leave, paid time‑off, and paid holidays.

Equal Opportunity Employment

Micron is proud to be an equal‑opportunity workplace and an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.