Director, Design Verification

Marvell Semiconductor, Inc.; California, Santa Clara (MO, CA); On-site; USD 176,000 - 265,000; Full time

Job summary

An established industry player is seeking a dynamic leader to manage a digital design verification team. This role involves overseeing the development of cutting-edge VLSI designs and ensuring uncompromised quality through innovative methodologies. The successful candidate will leverage their extensive experience to foster collaboration and drive continuous improvement within a global team. With a focus on impactful technology, this opportunity promises to shape the future of data infrastructure. Join a forward-thinking company committed to nurturing talent and delivering exceptional results in a rapidly evolving field.

Benefits

Flexible time off

401k

Year-end shutdown

Floating holidays

Paid time off to volunteer

Qualifications

• 5+ years of experience managing multidisciplinary teams.
• 12+ years in Design Verification for VLSI designs.

Responsibilities

• Build and manage a digital design verification team.
• Lead a highly technical team developing high complexity products.

Skills

Leadership

Problem Solving

Communication

Collaboration

VLSI Design Verification

RTL Coding

Verification Methodology

Timing Analysis

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

Verilog/SV

EDA Tools

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. We develop the architecture, collaborate on IP development, create the physical design, and work with the world's leading data center and enterprise companies to bring next generation networking to reality.

What You Can Expect

• Build and manage a strong digital design verification team.
• Improve the design methodology and flow.
• Makes decisions for talent management activities including hiring, assessing, rewarding, retaining, and developing engineers.
• Lead and be a part of highly technical team developing best-in-class high complexity products.
• Perform design review, code review, and apply tools to formally check/fix RTL against various design rules.
• Work with the verification team to define verification strategy, test-plan, analyze and sign-of verification coverage.
• Cooperate with Synthesis, DFT, STA, PnR to implement subsystems that meet challenging PPA requirements.
• Support Emulation, functional ATE, and silicon validation teams.

What We're Looking For

Managerial/Soft Skill Requirements:

• At least 5 years of experience in direct management of multidisciplinary teams including design, validation etc. (global team management is a plus)
• Proven leadership and problem solving skills focusing on uncompromised quality, innovation and continuous learning and improvement
• Strong communication, collaboration and teamwork skills and ability to work in global team environment
• Ability to build plans and define immediate and future needs based on project requirements

Technical Requirements:

• Bachelor's degree in Electrical Engineering or related fields and 12+ years of related professional experience in Design Verification for VLSI designs, OR Master's degree in Electrical Engineering or related fields with 10+ years of experience in Design verification for VLSI designs
• Hands-on micro architecture and RTL coding experience, Verilog/SV preferred.
• Strong knowledge of verification methodology, logic synthesis, DFT, and timing analysis.
• Excellent problem-solving skills and out-of-the-box thinking to oversee design failures.
• Experiences in PCIe/Ethernet is preferred.
• Experiences in UVM verification methodology is preferred.
• Very familiar with digital design methodologies, understand all stages of ASIC design flows, and experienced with state-of-the-art design verification EDA tools.

Expected Base Pay Range (USD)

176,930 - 265,000, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [e-mail].

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