Digital IC Design Engineer — IP Architect for SoCs

Texas Instruments; Bouchard (TX); On-site; USD 90,000 - 150,000; Full time

Job summary

Texas Instruments, within the Embedded Processors team, seeks an IP Design Engineer to design, architect and micro‑architect IPs enabling data movement, interconnect, safety, security and realtime functionality.

You will collaborate with SoC Design, Verification, Validation, Test, Systems and Marketing to convert concepts into high‑quality IP blocks and drive requirements from concept to silicon.

Qualifications

• Experience in IP design and architecture.
• Experience with RTL development and QC flows.
• Knowledge of IP verification plan development.
• Experience interfacing with external IP vendors.
• Support silicon bring-up and debug.
• Strong collaboration with cross-functional teams.

Responsibilities

• Be a key team member from IP requirement definition till release to market, working closely with all cross‑functional teams
• Define or enhance the micro‑architecture for digital IP blocks
• RTL development and QC flows to ensure superior IP quality
• Interface with 3rd party IP vendors and drive requirements and delivery milestones/quality
• Work closely with IP verification team to help build the IP verification plan and tests. Support functional debugs
• Support IP during silicon bring‑up activities, test program development, customer engagement and silicon/application debug
• Drive IP architectural optimization for area, power and performance improvements

Skills

IP design

RTL development

IP verification

Micro-architectures

Requirements gathering

Cross-functional collaboration

Tools

Verilog

SystemVerilog

SoC design

Job description

Texas Instruments, within the Embedded Processors team, seeks an IP Design Engineer to design, architect and micro‑architect IPs enabling data movement, interconnect, safety, security and realtime functionality.

You will collaborate with SoC Design, Verification, Validation, Test, Systems and Marketing to convert concepts into high‑quality IP blocks and drive requirements from concept to silicon.