Digital Design Engineer - Sr Staff

InvenSense Inc.; San Jose (CA); On-site; USD 60,000 - 75,000; Full time

Benefits offered by this job

Meal vouchers

Parking or transit pass

Supplemental health insurance

Job summary

InvenSense Inc. in San Jose, CA, part of the TDK Group, seeks senior engineers to lead ASIC design across RTL to layout for MEMS sensor products. You will interface with Analog/MEMS teams to optimize sensor architectures and verify digital IPs through silicon bring-up.

The role requires 10+ years (or a PhD with 8+ years) of experience, strong Verilog/SystemVerilog, and MATLAB/Simulink proficiency, with FPGA prototyping familiarity. Collaborative, detail-oriented candidates thrive here.

Qualifications

• Senior ASIC design experience with extensive RTL to layout exposure.
• Expertise in digital macro design for mixed-signal ASICs.
• Strong verification, timing, and power analysis skills.

Responsibilities

• Design, verify via simulations, and validate digital IPs in silicon/FPGA.
• Collaborate with Analog/MEMS teams to optimize sensor architectures.
• Contribute to verification plans at IP and system levels.
• Drive RTL-to-layout flow and assist top-level physical design.

Skills

Digital systems

Micro-architecture

Digital macros design

Logic synthesis

Formal verification

DFT (Design For Test)

Static timing analysis

Power analysis

ATPG

RTL simulations

Verilog

SystemVerilog

C++

Python

Perl

Makefile

MATLAB/Simulink

FPGA prototyping

Education

MSEE

PhD

Tools

MATLAB/Simulink

RTL/gate level simulations

FPGA prototyping flow

Job description

Founded in 2003, InvenSense Inc., a TDK Group Company, is the world’s leading provider of MEMS sensor platforms. InvenSense’s vision of Sensing Everything™ targets the consumer electronics and industrial markets with integrated Motion and Sound solutions. Our solutions combine MEMS (micro electrical mechanical systems) sensors, such as accelerometers, gyroscopes, compasses, and microphones with proprietary algorithms and firmware that intelligently process, synthesize, and calibrate the output of sensors, maximizing performance and accuracy. InvenSense’s motion tracking, audio and location platforms, and services can be found in many of the world’s largest and most iconic brands including smartphones, tablets, wearables, drones, gaming devices, internet of things, automotive products, and remote controls for smart TVs.

InvenSense is headquartered in San Jose, CA and has offices in Boston, China, Taiwan, Korea, Japan, France, Canada, Slovakia, and Italy. We’re looking for top-notch Engineers to join our global team. If you’re interested in being a part of our journey and helping us grow to become the leading provider of SoC platform solutions, we definitely want to hear from you.

This job opening applies for a position within the TDK InvenSense MEMS Microphones Business Unit.To operate effectively in the microphone product development field some audio specific competences are nice to have, such as audio signal processing techniques, speech recognition techniques, understanding and using audio interface protocols, knowledge of audio specific lab instrumentations such as the Audio Precision.

Job Description

1. Design, verify through simulation and validate in silicon/FPGA digital IPs for leading edge sensor products
2. Interface with Analog/MEMS design engineers both to define an optimize sensor architectures and to interface to analog sensors circuits
3. Contribute in verification plan definition, both at IP level and at top/system level
4. Drive the implementation flow from RTL to layout
5. Guide and support layout engineers for top level physical design

Qualification

1. MSEE with 10+ years (or PhD with 8+ years) of ASIC design experience
2. Thorough understanding of digital systems and micro-architecture trade-offs
3. Experience in design of digital macros in Mixed signal ASICs
4. Experience with logic synthesis, formal verification, Design For Testability, static timing analysis, power analysis, ATPG, Lint checks, cross domain checks, RTL and gate level simulations
5. Knowledge of techniques for:
   .Low power digital design
   .Digital signal processing blocks design
6. Experience with lab bench debugging and validation and silicon bring up
7. Knowledge of tools (Matlab/Simulink) for system modelization
8. Experience with FPGA prototyping flow and methodology
9. Effective interpersonal, teamwork, and communication skills.
10. Diligent, detail-oriented, and willing to take the initiatives for process and flow improvements
11. Proven teamwork skills
12. Excellent analytical and problem solving skills
13. Excellent oral and written communication skills
14. Conversant with some programmable languages such as Verilog, SystemVerilog, Perl/Python/Tcl scripts, Makefile and C++

The compensation package offered for this position is the following:

• Average RAL (Gross Annual Salary) from 60K to 75K €.
• Variable compensation depending on personal and Corporate performances: of up to 35%
• Benefits: €9 meal vouchers, car parking or public transport pass, supplemental health insurance.

The salary range is relative to the specified job grade offered, which may vary based on the candidate's actual experience.