Digital Design Engineer

Acceler8 Talent; United States; Remote; USD 220,000 - 250,000; Full time

Job summary

Acceler8 Talent is seeking a Senior ASIC Design Engineer to join a pioneering AI hardware company focused on efficient AI inference acceleration. The role encompasses architecting and implementing hardware designs while collaborating with top engineers. Candidates will contribute significantly by addressing complex challenges at the intersection of AI and hardware, emphasizing skills in RTL programming and hands-on experience with FPGA/ASIC tools.

Qualifications

• 5+ years of experience in hardware systems design.
• Strong knowledge of ASIC and FPGA programming.
• Hands-on experience in PCIe PHY and controller IP integration.

Responsibilities

• Design and oversee hardware architecture evaluations.
• Code RTL modules in Verilog/SystemVerilog.
• Perform hardware testing, debug, and verification.

Skills

RTL programming

Verilog/SystemVerilog

Python

Agile development methodologies

Education

B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science

Tools

FPGA/ASIC development tools

Job description

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This range is provided by Acceler8 Talent. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$220,000.00/yr - $250,000.00/yr

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Building North American Semiconductor and Photonic design teams

Acceler8 Talent is working with an innovative AI hardware company delivers energy-efficient AI inference acceleration, supporting any neural network model from the edge to the cloud. They are looking for a Senior ASIC Design engineer, anywhere in the US or Canada!

They are breaking through the barriers to running AI workloads faster, cooler, and more cost-effectively with their AI accelerator ICs and PCIe cards.

Founded in 2018, this company is on a mission to bring AI out of data centers and into the hands of users at the network edge. Their unique at-memory architecture for deep learning places processing right next to the memory, cutting down on data movement and power consumption. Their hardware allows enterprises to operate AI workloads anywhere, without being tethered to a data center. While others promise solutions, this company delivers real products.

They have raised over $200m in funding and have already sold their product to several smart clients who want to get in at ground 0.

We’re looking for best in class engineers to join our existing top-notch team. When you join Untether AI, you will be part of the team that creates innovative hardware and delivers industry leading AI performance and efficiency. Utilizing non Von Neumann techniques, you will help propel sustainable AI inference.

As part of this talented team of engineers, you are able to - and are excited to - architect, implement, verify and productize custom hardware designs. Being on our team means collaborating with an extremely bright group of people while tackling tough and interesting problems at the intersection of AI and hardware.

To help grow our organization, we are looking for an RTL Designer to contribute to a team developing IP for both ASICs and FPGAs. The ideal candidate is a strong communicator, creative, a critical thinker, and able to analyze and resolve complex issues.

Responsibilities

• Design, propose, and oversee the analysis/evaluation of hardware architectures
• Design and code RTL modules written in Verilog/SystemVerilog
• Simulate and perform hardware-based testing, debug, and verification
• Scripting and basic software development in support of hardware design
• Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment

Requirements:

• B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science
• 5+ years of experience in hardware systems design, analyzing and improving RTL hardware performance and area as well as lab bring-up
• FPGA/ASIC development environment tools expertise, including design, implementation and debug
• Strong knowledge with RTL programming languages Verilog/SystemVerilog (preferred), or VHDL
• Ability to read and write code in Python (C, C++ are assets)
• Hands on experience in PCIe PHY and controller IP integration and bring-up

Preferred Skills & Experience:

• Deep experience with ASIC and FPGA programming including timing closure, resource management, and using IP libraries highly preferred
• Working experience with PCIe, UCIe, and HBM will be an asset
• Experience with Agile development methodologies
• Experience in technical leadership of small teams

If you feel your background and skillset are well aligned with what this company is looking for, please feel free to apply or reach out to [e-mail]

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Design and Engineering

• Industries

  Computer Hardware Manufacturing and Software Development

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