Digital Circuit Design Engineer

Apple; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Apple in Austin, TX seeks a design engineer to design and implement SRAM circuits. You will collaborate with an exceptional logic/architecture team to optimize power, timing, area and yield, perform schematic captures, simulations and margin verifications, and support post-silicon productization.

Proficiency with CAD tools and SRAM design is required; Master’s degree preferred. Join a team delivering cutting-edge memory solutions in a fast paced environment with strong emphasis on quality and

Qualifications

• Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.
• Proficiency with CAD tools for design entry and analysis (Cadence Virtuoso, Spice, Layout tools, Skill, Model Sim, Digital P&R).
• Experience debugging simulation failures and chip simulations for logical and timing verification.
• Knowledge of device physics and transistor-level circuit optimization.
• SRAM design experience to build and evaluate memory circuits.
• Ability to analyze circuits and SPICE simulations to ensure robust operation.
• Experience with waveform viewers (SpiceExplorer or WaveView) to verify circuit logic and timing.
• Experience with static timing analysis of SRAM designs using NanoTime, PrimeTime or similar.

Responsibilities

• Design and implement custom digital circuits for SRAM.
• Formulate design specifications with the architecture/logic team.
• Define architectures optimizing power, timing, area and yield.
• Perform schematic capturing, simulations/analysis, and margin verifications.
• DFT modeling and functional equivalency verification.
• Collaborate with layout to produce optimal GDS.
• Verify extracted GDS meets design specs; backend verification of layout.
• Write RTL and validate use-cases against schematics.
• Support post-silicon activities to enable productization.

Skills

SRAM design

Circuit analysis

Timing verification

Device physics knowledge

Education

Master's degree in Electrical and Computer Engineering or related field

Tools

Cadence Virtuoso

Spice

Layout tools

Skill language

ModelSim

Digital P&R

compilers

simulators

WaveView

SpiceExplorer

PrimeTime

NanoTime

Job description

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Design and implement custom digital circuits for SRAM design. Work with an extraordinary logic/architecture team to formulate design specifications. Define architecture/topologies optimizing for power, timing, area and yield. Perform schematic capturing, simulations/analysis, and margin verifications. Responsible for functional equivalency and DFT modeling. Work with layout team to create optimal GDS. Verify extracted GDS meets design specifications. Responsible for backend verification of layout, including IR/Electromechanical analysis. Write RTL, validating use‑cases, verifying against design schematics. Support post‑silicon effort to enable productization. 40 hours/week.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.

• Utilizing CAD tools including Cadence Virtuoso, Spice, Layout tools, Skill language, Model Sim, Digital P&R, compilers, or simulators for design entry and analysis.
• Debugging simulation failures and chip simulations on CAD software for logical and timing verification.
• Utilizing knowledge of device physics and transistor for circuit optimization.
• SRAM design skills to build and evaluate memory circuits.
• Analyzing circuits and SPICE simulation to ensure robust operation.
• Utilizing waveform viewers including SpiceExplorer or WaveView to verify circuit logic and timing.
• Static Timing Analysis of an SRAM design, using NanoTime, PrimeTime or similar for static timing verification.

Preferred Qualifications

N/A