DFx Methodology Architect

AMD; San Jose (CA); Hybrid; USD 140,000 - 210,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD is seeking a DFx IP Architect to join a small expert team in San Jose, CA. You will define DFx architecture for next-gen monolithic and stacked SoCs, and collaborate with IP teams to drive timing, validation, and yield improvements.

Candidates should have strong RTL design, timing constraints, and verification experience, plus programming skills in Perl, TCL, and Python. This hybrid role emphasizes innovation, collaboration, and solving challenging DFx problems.

Qualifications

• RTL design, timing constraints and design methodologies.
• Design qualification – STA, RTL-DRC, CDC, RDC, Constraints checking.
• Programming experience – Perl, TCL, Python.
• Design verification – Verilog simulation, coverage analysis, assertions.
• Prior knowledge of Scan design, ATPG, Memory BIST, Repair and harvesting for yield is a plus.

Responsibilities

• Define constraints and dependencies for IPs based on block interfaces, power supply & configuration requirements.
• Address and improve efficiency of timing, PnR, DRC and integration methodologies for DFx IPs.
• Develop new IPs and methodologies, including process characterization IP for test-vehicles.
• Define DFx Architecture for AMD’s next generation monolithic and stacked SoC product families.
• Work with functional IP teams on integration, analysis and qualification methodologies for a growing number of DFx IPs, tools and flows.

Skills

RTL design

timing constraints

design methodologies

Perl

TCL

Python

Verilog simulation

assertions

IP integration

DFx concepts

Education

Bachelor's or Master's in computer engineering / Electrical Engineering

Tools

Verilog

STA tooling

RTL-DRC

ATPG

Memory BIST

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

Our global team is growing, and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything.

THE PERSON:

This position invites candidates to join a small team of experts, inventing and implementing original solutions, addressing challenging DFx problems in some of the industry’s largest and most complex SOCs. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Define constraints and dependencies for IPs based on block interfaces, power supply & configuration requirements
• Address and improve efficiency of timing, PnR, DRC and integration methodologies for DFx IPs
• Develop new IPs and methodologies, including process characterization IP (timing, defectivity etc.) for test-vehicles
• Define DFx Architecture for AMD’s next generation monolithic and stacked SoC product families, including testability, debug, characterization, repair and yield
• Work with functional IP teams on integration, analysis and qualification methodologies for a growing number of DFx IPs, tools and flows

PREFERRED EXPERIENCE:

• RTL design, timing constraints and design methodologies
• Design qualification – STA, RTL-DRC, CDC, RDC, Constraints checking
• Programming experience – Perl, TCL, Python
• Design verification – Verilog simulation, coverage analysis, assertions
• Prior knowledge of Scan design, ATPG, Memory BIST, Repair and harvesting for yield are a plus

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

This role is not eligible for visa sponsorship.

#LI-CJ3

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental and/or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.