DFT Architect

Advanced Micro Devices; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

Advanced Micro Devices in San Jose, California is seeking a DFT Architect to drive DFT architecture for Scan, MBIST, PHY, and high‑speed IOs across future AMD products.

You will work with design architecture, DFT/DFX, and physical design teams, ensuring manufacturability and early silicon readiness while collaborating with cross‑functional teams across continents.

Qualifications

• Experience in DFT pre and post silicon cycles and test architectures.
• Design experience for chip‑level DFT including Scan & Scan Compression.
• Knowledge of FPGA, Verilog, synthesis, STA and verification.
• Experience with post‑silicon debug and bench equipment.

Responsibilities

• Define DFT architecture across IP/SoC/FPGA logics and ensure manufacturability.
• Collaborate with design, verification, and manufacturing/test teams.
• Drive DFT activities across architecture, design implementation, and test.

Skills

DFT engineering

MBIST

Verilog

SoC design

FPGA logic

post-silicon debug

Education

MS/Ph.D. in Electrical/Computer Engineering

Tools

Tessent SSN

ATPG tools

Oscilloscope

Logic analyzer

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

THE ROLE:

As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high‑speed/high‑density IOs, communication controllers and FPGA logics of future AMD products. The role involves working with design architecture, design DFT/DFX, design block owners and physical design teams with ATE manufacturing environment, silicon debug, product quality and test cost perspectives. The DFT architect is expected to apply past technical knowledge, learn new cutting‑edge technologies and collaborate with teams to arrive at best manufacturable solution. The DFT architect will ensure that DFT implementation is completed by architecture design specifications. This is the role of overseeing early architecture design definition to successful silicon high‑volume production.

THE PERSON:

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization.

KEY RESPONSIBILITIES:

• Promote ATE & production test environment, test cost and test quality enhancements in future AMD products through DFT architecture definitions and specifications
• Manage DFT activities across architecture, design implementation, verification, and test implementation for new products.
• The role is in AMD global quality and operation organization driving best manufacturing test solution through early product definition and pre & post silicon activities
• Work closely with design teams and make sure DFT structures are correctly implemented.
• Drive internal DFT teams to correctly implement and create test solutions
• Drive firmware driven test solutions
• Plan for diagnosability and yield improvement

PREFERRED EXPERIENCE:

• Significant DFT engineering experience through DFT pre and post silicon cycles
• Experience in creating and implementing complex chip‑level DFT architecture
• Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
• Experience with DFT tools, ATPG (Stuck‑At, At‑Speed, Path‑Delay) and scan compression.
• Strong MBIST knowledge
• Experience in PHY, high‑speed IO, digital communication and functional test development
• Knowledge of Tessent Streaming Scan Network SSN and hand‑on experience is a big plus
• Good understanding of Verilog, synthesis, physical implementation and STA
• Good understanding of verification methodology
• Knowledge of FPGA logic, synthesis and design flow is a plus
• Knowledge of embedded design and firmware methodology is a plusExperience with post‑silicon debug and bench equipment (e.g., oscilloscope and logic analyser)
• Good communication skills and works well in a group environment that spans across continents

ACADEMIC CREDENTIALS:

• MS or Ph.D. in Electrical/Electronic/Computer Engineering

LOCATION:

San Jose, California, United States

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.