Design Verification Sr Staff Engineer in District 7

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 90,000 - 150,000; Full time

Job summary

Join a forward-thinking company at the forefront of technology innovation, where you will play a crucial role in the development of high-performance silicon chips. As a Design Verification Engineer, you will define verification plans, build environments, and apply advanced techniques to ensure the reliability of cutting-edge IP solutions. Collaborate with a diverse team of experts and contribute to innovations in industries like AI, autonomous vehicles, and IoT. This is an exciting opportunity to grow in a supportive environment while making a significant impact on the future of technology.

Benefits

Health benefits

Wellness programs

Financial benefits

Continuous learning opportunities

Qualifications

• 5+ years of experience in design verification in the industry.
• Proficiency in developing System Verilog, UVM, or similar HDL-based test environments.
• Strong knowledge of industry protocols and tools.

Responsibilities

• Defining verification plans and building verification environments for designs.
• Writing test cases and applying advanced verification techniques.
• Collaborating with cross-functional teams to ensure quality.

Skills

Design Verification

ASIC Design Verification

Analytical Skills

Communication Skills

Collaboration Skills

Programming in C

Programming in Python

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Bachelor's in Computer Science

Master's in Computer Science

Tools

Verilog

System Verilog

UVM

AMBA

PCI-Express

CXL

Ethernet

HBM

DDR

Job description

Alternate Job Titles:

• ASIC Verification Senior Staff Engineer
• Senior Staff Digital Verification Engineer
• Senior Staff ASIC Digital Design Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled Design Verification Engineer with a passion for innovation and excellence. You thrive in dynamic environments and are excited about pushing the boundaries of technology. With your expertise in ASIC Design Verification for IP, Subsystem, or SoC, you are ready to contribute to a team that is at the forefront of the industry. You have a strong background in developing verification plans, building verification environments, and applying advanced verification techniques. Your experience with industry protocols and tools, along with your programming skills, makes you a valuable asset to any team. You are a proactive team player with excellent analytical, communication, and collaboration skills, eager to grow and develop in a supportive and diverse environment.

What You’ll Be Doing:

• Defining verification plans and building verification environments for block/sub-system level designs using Verilog, System Verilog, and UVM.
• Writing test cases, checkers, and coverage that implement the verification test plan.
• Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
• Working closely with RTL designers and other parts of our global verification team to debug failures.
• Collaborating with cross-functional teams to ensure the highest quality of IPs and subsystems.
• Continuously improving verification methodologies and processes to enhance efficiency and effectiveness.

The Impact You Will Have:

• Contributing to the development of high-speed silicon-proven interface IP solutions in the latest process technology.
• Enabling innovations in cutting-edge industry verticals including Artificial Intelligence, Autonomous Vehicles, High-Performance Compute, Cloud, 5G Mobile, and IoT.
• Ensuring the reliability and performance of IPs and subsystems used in tens of millions of SoCs.
• Driving technological advancements that impact billions of people worldwide.
• Enhancing Synopsys' reputation as the top IP provider with the broadest portfolio and most advanced technology.
• Supporting the continuous growth and development of a diverse and talented global team.

What You’ll Need:

• Bachelor's or Master's degree in Electrical Engineering or Computer Science.
• 5+ years of experience in design verification in the industry.
• Knowledge of protocols such as AMBA, PCI-Express, CXL, UCIe, Ethernet, HBM, DDR.
• Experience with industry-standard simulators, revision control systems, and regression systems.
• Proficiency in developing System Verilog, UVM, or similar HDL-based test environments.
• Programming skills in HDL, Verilog, System Verilog, C, Perl, Python.

Who You Are:

You possess excellent analytical skills, and you are a proactive and self-motivated team player. Your strong oral and written communication skills enable you to collaborate effectively with global teams. You are passionate about continuous learning and development, and you bring a positive attitude and enthusiasm to your work.

The Team You’ll Be A Part Of:

You will be joining the newly created Subsystem Verification Team in Ho Chi Minh City, Vietnam. This team is made up of industry-leading professionals who are passionate about innovation and excellence. The team is diverse, enthusiastic, and supportive, offering a fun culture and ample opportunities for growth and development. You will work alongside experts in the field, empowered by Synopsys' EDA ecosystem, to create high-performance silicon chips and software content.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.