Design Verification Engineer | Sensing

Texas Instruments; Dallas (TX); On-site; USD 90,000 - 140,000; Full time

Job summary

Texas Instruments is seeking a Design Verification Engineer in Dallas to work on advanced mixed-signal sensor circuits and high-performance digital interfaces. You will contribute to digital and AMS verification, develop test plans, and create SystemVerilog testcases for next-generation designs.

You will drive regression, risk assessment, and verification flow improvements, collaborating with design and systems teams to close spec gaps and ensure robust, testable designs in a fast-paced

Responsibilities

• Develop detailed Verification/Test plans using specifications to cover all digital/analog functionality/features of a mixed-signal chip for our next generation designs.
• Develop SystemVerilog chip-level testcases based on the verification plan.
• Simulation, Testcase debug and Verification closure for the digital/analog functionality of Mixed-signal chips, at chip-level in digital and AMS environment.
• Finding design bugs with break-the-design mindset and ensuring design is bug-free and robust.
• Develop SystemVerilog based behavioral models for the analog blocks and integrate them in the chip-level verification environment.
• Running regressions and DV closure activities.
• Work closely with design and systems teams to review/close spec gaps and design bugs, as they arise.
• Design for testability using ad-hoc, Full scan,IDDQ, VBOX, ATPG, BIST
• Drive documentation, reviews and verification flow improvement strategies.
• Be proactive in risk assessment and drive solutions to mitigate them.

Job description

Change the world. Love your job.
Texas Instruments is seeking Design Verification Engineer. In this position, you will be working on advanced mixed-signal sensor circuits using state-of-the art process technology, as well as be involved in the digital and AMS verification of high-performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.

In this role, your responsibilities will include the following.

• Develop detailed Verification/Test plans using specifications to cover all the digital/analog functionality/features of a mixed-signal chip for our next generation designs.
• Develop SystemVerilog chip-level testcases based on the verification plan.
• Simulation, Testcase debug and Verification closure for the digital/analog functionality of Mixed-signal chips, at chip-level in digital and AMS environment.
• Finding design bugs with break-the-design mindset and ensuring design is bug-free and robust.
• Develop SystemVerilog based behavioral models for the analog blocks and integrate them in the chip-level verification environment.
• Running regressions and DV closure activities.
• Work closely with design and systems teams to review/close spec gaps and design bugs, as they arise.
• Design for testability using ad-hoc, Full scan,IDDQ, VBOX, ATPG, BIST
• Drive documentation, reviews and verification flow improvement strategies.
• Be proactive in risk assessment and drive solutions to mitigate them.