Design Verification Engineer - Machine Learning Accelerators

Meta; Redmond (WA); On-site; USD 173,000 - 249,000; Full time

Job summary

A leading technology company is seeking a Design Verification Engineer specializing in Machine Learning Accelerators. In this role, you will work with top researchers and engineers to develop and validate cutting-edge machine learning algorithms and systems. Your expertise in digital design and verification will be crucial in optimizing products for mixed reality and smart devices. This position offers a competitive salary and the opportunity to be part of groundbreaking projects in augmented reality.

Qualifications

• 10+ years of hands-on experience in SystemVerilog/UVM methodology.
• Experience in IP/sub-system and/or SoC level verification.

Responsibilities

• Develop industry-leading Machine Learning IP’s optimized for Mixed Reality.
• Define and lead execution of detailed test plans for modules.
• Collaborate with cross-functional teams to ensure design quality.

Skills

SystemVerilog

C/C++

Python

TCL

Perl

Shell

Education

Bachelor's degree in Computer Science

Bachelor's degree in Computer Engineering

Master's in Electrical Engineering

Tools

EDA tools

Mercurial

Git

Job description

Design Verification Engineer - Machine Learning Accelerators

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Design Verification Engineer - Machine Learning Accelerators

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Join to apply for the Design Verification Engineer - Machine Learning Accelerators role at Meta

This range is provided by Meta. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$173,000.00/yr - $249,000.00/yr

Reality Labs focuses on delivering Meta's vision through Augmented Reality (AR) and Smart Devices. Compute power requirements of these devices require custom silicon. Meta’s Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day, and smart devices that provide assistance and super powers in our day-to-day activities. We believe the only way to achieve our goals is to look at the entire stack, through algorithms to architecture, transistors to firmware. As a Design Verification Engineer at Meta’s Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art machine learning algorithms. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art machine learning IPs.

Design Verification Engineer - Machine Learning Accelerators Responsibilities:

• Work with cross-functional leads, including product managers, systems architects, researchers, and software architects, to develop industry leading Machine Learning IP’s optimized for Mixed Reality and Smart Devices and use-cases, defining verification methodologies for each of the different core IPs.
• Define, track, and lead the execution of detailed test plans for the different modules and top levels.
• Implement scalable test benches including checkers, reference models, assertions in System Verilog.
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
• Collaborate with cross-functional teams such as Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality across pre- and post-Silicon product lifecycle.
• Support hand-off and integration of developed subsystems/IP blocks into larger SOC environments.
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
  
  

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 10+ years of hands-on experience in SystemVerilog/UVM methodology and C/C++ based verification.
• 10+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
• Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
• Track record of 'first-pass success' in ASIC development cycles.
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  
  

Preferred Qualifications:

• Masters in Electrical Engineering or Computer Science.
• Experience with Design verification/validation of machine learning applications and accelerators.
• Experience with revision control systems like Mercurial(Hg), Git.
• Experience with low power design.
• FPGA/emulation debug experience.
• Experience in verification of numerical compute based designs.
• Experience with Software/Hardware Co-design at firmware, ISA, and application level
  
  

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

$173,000/year to $249,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Seniority level

• Seniority level

  Not Applicable

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Technology, Information and Internet

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