Design Verification Engineer | BCP

118-WW TMG MFG OPS; Knoxville (TN); On-site; USD 100,000 - 140,000; Full time

Job summary

Texas Instruments in Knoxville seeks a Design Verification Engineer to drive verification strategy for analog and mixed-signal ICs, collaborating with digital design and systems teams.

You will develop test benches and RTL/GLS simulations, run coverage regressions, track status, and contribute to DV methodology improvements.

Qualifications

• Bachelor's degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering, or related field

Responsibilities

• Develop detailed verification plans and build test benches
• Run coverage regressions to meet defined coverage goals
• Track and communicate verification status, issues, and concerns
• Work with regression tools and develop scripts to submit cases for regression analysis
• Contribute to continuous improvements for DV strategy, tools, methods, and flows

Skills

SystemVerilog

UVM

Testbenches

Scripting

DV methodology

Coverage-driven verification

RTL simulation

Python

Tcl

Perl

Education

Bachelor's degree in Electrical Engineering or related

Tools

Cadence Xcelium

Synopsys VCS

Job description

Change the world. Love your job.

Texas Instruments is seeking a Design Verification Engineer to join our Analog Power Products organization in Knoxville. In this role, you will develop and execute verification strategies that ensure first-pass silicon success for next-generation analog and mixed-signal ICs across industrial, automotive, and consumer applications.

As a Design Verification Engineer, you will work across the full verification cycle – from developing detailed verification plans and building test benches through running coverage regressions, tracking closure, and contributing to continuous improvements in DV methodology – collaborating closely with digital design and systems engineering teams.

Responsibilities include:

• Develop detailed verification plans while working closely with the design and system team to ensure first-pass silicon success
• Develop test benches, tests, and simulations at RTL and gate-level (GLS) for the entire chip
• Run coverage regressions to meet defined coverage goals
• Track and communicate verification status, issues, and concerns
• Work with regression tools and develop scripts to submit cases for regression analysis
• Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods, and flows

Minimum requirements:

• Bachelor's degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering, or related field
• 3+ years of experience in design verification or a related role

Preferred qualifications:

• Experience with functional verification methodologies including simulation, assertions, and coverage-driven verification
• Proficiency in SystemVerilog and UVM-based testbench development
• Experience with Mixed Signal verification a plus
• Experience with System Verilog real number models a plus
• Familiarity with RTL simulation tools (Cadence Xcelium, Synopsys VCS, or equivalent)
• Experience with gate-level simulation and timing-aware verification flows
• Scripting skills for regression automation and verification flow development (Python, Tcl, or Perl)
• Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
• Strong verbal and written communication skills
• Demonstrated strong interpersonal, analytical, and problem-solving skills
• Ability to work in teams and collaborate effectively with people in different functions
• Ability to take the initiative and drive for results