Design Verification Architect

Actalent; Morrisville (NC); On-site; USD 150,000 - 250,000; Full time

Benefits offered by this job

Medical dental vision

Bonus structure

Job summary

Actalent seeks a senior verification leader to own the architecture for complex mixed-signal PMICs and to drive UVM environments from ground up in a new Morrisville center.

The role requires expert SystemVerilog/UVM, RTL verification, and firmware integration experience, with mentorship responsibilities across digital and analog teams. This is a fully onsite position in Morrisville, NC.

Qualifications

• Expert in verification architecture for mixed-signal ICs and PMICs.
• Proven ability to architect and build multiple UVM environments from scratch.
• Deep SystemVerilog, UVM, constrained-random verification and coverage closure expertise.
• Experience integrating embedded firmware into verification environments.
• Mentor engineers and lead complex verification programs across teams.

Responsibilities

• Own the verification architecture and strategy for complex mixed-signal PMICs.
• Design and build advanced UVM environments from ground up with testbenches, scoreboards, and coverage models.
• Define scalable verification methodologies for multiple products and programs.
• Lead verification planning, regression, and tape-out readiness.
• Provide technical direction across digital and analog verification domains.

Skills

UVM

SystemVerilog

Power management

Python

TCL

Perl

Job description

Description

We are partnering with a rapidly growing semiconductor organization that is making a significant investment in next-generation power delivery technologies for AI infrastructure, high-performance computing, and intelligent edge systems. This role offers the opportunity to serve as a technical leader within a newly established U.S. engineering center, helping define verification methodology and architecture for complex mixed-signal power management ICs. The successful candidate will drive the development of advanced UVM-based verification environments from the ground up, collaborate closely with analog, digital, firmware, and system architects, and influence verification strategy across multiple high-impact products. Beyond hands‑on technical leadership, this position provides a rare opportunity to build scalable verification infrastructure, mentor engineers, and shape the long‑term direction of a growing verification organization. Ideal candidates will have a track record of architecting verification environments from scratch, driving coverage closure, and solving challenging verification problems at the system, subsystem, and block levels.

Core Responsibilities

• Own the verification architecture and strategy for complex mixed-signal and power management ICs.
• Design and build advanced UVM verification environments from the ground up, including testbench architecture, reusable components, stimulus generation, scoreboards, assertions, coverage models, and regression infrastructure.
• Define scalable verification methodologies that can be applied across multiple products and development programs.
• Establish verification plans spanning the block, subsystem, and full-chip levels.
• Lead verification from early requirements and test planning through regression, coverage closure, and tape‑out readiness.

UVM and SystemVerilog Development

• Develop sophisticated, coverage-driven verification environments using SystemVerilog, UVM, and object-oriented methodologies.
• Create reusable agents, monitors, drivers, scoreboards, protocol checkers, assertions, and functional coverage models.
• Develop constrained-random stimulus and comprehensive test strategies for complex operating modes, interactions, and corner cases.
• Establish efficient regression, debug, and failure-analysis methodologies.
• Provide technical direction when resolving challenging verification issues across digital and analog domains.

Mixed‑Signal and Firmware Verification

• Develop verification strategies that validate the interaction between digital RTL, analog behavioral models, embedded firmware, and system-level functionality.
• Integrate embedded software into UVM-based environments to validate hardware and firmware behavior prior to silicon.
• Build co-simulation environments for processor-based and mixed-signal architectures.
• Partner with firmware and design teams to identify interface risks, system-level corner cases, and potential failure conditions early in the development lifecycle.
• Apply AMS, DMS, RNM, or comparable methodologies to improve verification speed, scalability, and coverage.

Power Management IC Verification

• Apply verification expertise to sophisticated power management functions such as voltage regulation, power sequencing, multi-phase control, monitoring, telemetry, and protection features.
• Collaborate closely with analog and digital designers to understand circuit behavior, operating modes, transient conditions, and failure mechanisms.
• Translate system and circuit-level requirements into meaningful verification scenarios rather than relying solely on traditional digital verification approaches.
• Develop verification strategies that accurately represent real-world power‑management behavior and system interactions.

Skills

Design verification, UVM, systemverilog, power management, python, tcl, perl

Top Skills Details

• Extensive semiconductor verification experience, typically gained through 10 or more years in increasingly complex technical roles, or an equivalent level of demonstrated expertise.
• Experience operating at a Staff, Principal, Architect, or Technical Lead level.
• A proven track record of personally architecting and building multiple UVM verification environments from scratch.
• Deep expertise in SystemVerilog, UVM, constrained-random verification, assertions, functional coverage, and coverage closure.
• Strong understanding of the complete verification lifecycle, from requirements analysis and test planning through regression and signoff.
• Experience verifying complex mixed‑signal ICs or systems involving tightly coupled analog and digital functionality.
• Practical experience with AMS, DMS, RNM, behavioral modeling, or comparable mixed-signal verification methodologies.
• Experience integrating embedded firmware or processor-driven functionality into hardware verification environments.
• Understanding of embedded processor architectures and hardware-software interaction.
• Strong communication, collaboration, mentorship, and technical decision-making skills.

Additional Skills & Qualifications

• Experience verifying power management ICs, voltage regulators, DC/DC converters, multi-phase control systems, power sequencing, protection circuitry, or related architectures.
• Experience delivering mixed‑signal verification within a complex semiconductor product environment.
• Familiarity with leading simulation, mixed‑signal, waveform‑debug, and analog‑design platforms.
• Experience applying digital mixed‑signal and real-number modeling techniques.
• A history of developing reusable verification frameworks that support multiple products or engineering teams.
• Proficiency with scripting and automation tools such as Python, Perl, Tcl, shell scripting, or Make.
• Experience mentoring engineers and providing technical leadership across complex verification programs.

Experience Level

Expert Level

Job Type & Location

This is a Permanent position based out of Morrisville, NC.

Pay And Benefits

The pay range for this position is $150000.00 - $250000.00/yr.
Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors.
Medical, dental, vision, bonus structure, etc

Workplace Type

This is a fully onsite position in Morrisville,NC.

Application Deadline

This position is anticipated to close on Sep 17, 2026.

About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email [e-mail] for other accommodation options.

San Francisco Fair Chance Ordinance: Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.

Massachusetts Lie Detector: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Use of Artificial Intelligence (AI): We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.