Design For Test Engineer IV (IC)

Arrow Electronics; San Jose (CA); On-site; USD 112,000 - 171,000; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

401k with match

Paid Time Off

Tuition Reimbursement

Job summary

Arrow Electronics seeks an experienced Design For Test Engineer IV (IC) in San Jose, CA. You will lead DFT for advanced networking chips, perform scan insertion, ATPG, and MBIST across multi‑million gate SoCs, and verify JTAG flows on silicon.

You will collaborate with RTL, verification, and design teams, writing scripts in Perl/Shell/TCL to automate flows and debug complex issues. This is a full‑time on‑site role with growth opportunities.

Qualifications

• 5–7 years of experience in DFT for multi‑million gate count SoCs.
• Proficient in Scan-Insertion, ATPG, GLS and pattern simulations.
• Experience with MBIST insertion and IEEE 1149.1 JTAG verification.

Responsibilities

• DFT implementation for 3nm and 5nm networking chips.
• RTL checks for scan‑insertion compatibility using Spyglass.
• Scan‑Insertion using Tessent TestKompress.
• ATPG pattern generation with/without timing.
• Pattern simulation with timing across corners using VCS.
• Mismatch debugging with Verdi.
• Scripting with Perl, Shell, TCL to augment the flow.
• MBIST insertion and verification on top blocks.
• Silicon bring‑up and debug for block and top.
• IEEE 1149.1 JTAG insertion and verification.

Skills

DFT

Scan-Insertion

ATPG

GLS

MBIST

JTAG Insertion

Perl

Shell

TCL

Networking SoCs

Education

B.Tech/M.Tech in Microelectronics/Electronics

Tools

Mentor Tessent

Cadence Modus

Synopsys Tetramax

Verdi

VCS

Job description

Position:

Design For Test Engineer IV (IC)

Job Description:

What You'll Be Doing:

• DFT implementation for 3nm and 5nm Networking chips, IP DFT work
• RTL checks for scan-insertion compatibility using Synopsys Spyglass
• Scan-Insertion using Tessent TestKompress
• ATPG pattern generation:
• Compressed and Uncompressed Mode
• Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax
• Pattern Simulation:
• Without timing, With timing for different corners
• Tools: VCS
• Mismatch debug using Verdi
• Scripting with Perl, Shell, TCL:
• DAeRT - DFT flow enhancement/automation in project
• Makefile enhancement using extended scripts and targets for flow enhancement
• MBIST Insertion and Verification:
• MBIST Insertion and Verification done on block on top
• Silicon debug and bring-up done for block and top
• IEEE 1149.1 JTAG Insertion and verification

What We Are Looking For :

• 5 – 7 Years of experience in DFT
• Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing)
• MBIST Insertion and Verification
• Experience in IEEE 1149.1 JTAG Insertion and verification
• Scripting languages like Perl, Shell, TCL
• Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes
• Tools: Mentor Tessent
• B. Tech, M.Tech in Microelectronics/Electronics
• Excellent communicator
• Low power DFT

What’s In It for You:

• Medical, Dental, Vision Insurance
• 401k, With Matching Contributions
• Short-Term/Long-Term Disability Insurance
• Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
• Paid Time Off
• Tuition Reimbursement
• Growth Opportunities
• And more!

Work Arrangement Fully On-Site:

Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.

Location:

San Jose, CA

About eInfochips:

eInfochips (https://www.einfochips.com/) , an Arrow company (Fortune #109), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow’s $33B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries & verticals.

EEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy) (https://static4.arrow.com/-/media/Arrow/Files/PDF/2023-Arrow-EEO-United-States.pdf)

Annual Hiring Range/Hourly Rate:

$112,200.00 - $170,500.00

Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.

Location:

US-CA-San Jose, California (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services

EEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy) (https://cdn.phenompeople.com/CareerConnectResources/ARELUS/documents/EqualEmploymentOpportunityPolicy_UnitedStates_2024-1713302215740.pdf)

All Arrow job postings are for existing job vacancies . We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Arrow Electronics, Inc.'s policy is to provide equal employment opportunities to all qualified employees and applicants without regard to race, color, religion, age, sex, marital status, gender identity or expression, sexual orientation, national origin, disability, citizenship, veran status, genetic information, or any other characteristics protected by applicable state, federal or local laws. Our policy of equal employment opportunity and affirmative action applies to all employment decisions personnel policies and practices, or programs.