Design Automation Engineer (TFM/EDA)

Intel Corporation; Folsom (CA); Hybrid; USD 118,000 - 227,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel Corporation in California is seeking a seasoned Silicon Design Automation Engineer to support design environments, PDKs, and EDA tooling for external foundry customers. You will install, maintain, and provide technical support for design automation scripts, flows, and licenses, while ensuring scalable compute resources.

You will collaborate with PDK/library and flow teams, engage with EDA providers, and create automation to streamline installation and deployment of design environments.

Qualifications

• US citizenship is required and TS/SCI clearance may be needed.
• BS or MS in Electrical/Computer Engineering with practical tool/flow experience.
• Experience with EDA tools and design methodologies (TFM) and debugging.
• Proficiency with Verilog/VHDL and scripting (Tcl, Perl, Python).
• Linux experience with bash/tcsh.

Responsibilities

• Resolve designer's tool/methodology issues toward TapeOut.
• Provide ramp-up support through training and documentation.
• Interact with EDA providers to ensure tool features meet project needs.
• Collaborate with PDK/library, flow development, and product design teams; help debug compute issues.
• Create automation scripts and checkers for design-environment installation.
• Support integration of new tools/methods into workflows for scalability.
• Communicate effectively to maintain high quality standards.

Skills

US Citizenship

Security Clearance TS/SCI

Electrical Engineering

Computer Engineering

EDA tools

Debugging

Verilog/VHDL

Tcl

Perl

Python

Linux Bash

tcsh

TapeOut

PDK/Flows

Cheetah

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

EDA tools

PDK installation

Cheetah

Job description

Job Details

At Intel Foundry Automation - Government Programs, we believe in empowering our employees with the tools and opportunities to excel, grow, and make a real impact. If you're a seasoned Silicon Design Automation Engineer with proficiency in Design TFM (Tools, Flows, Methodology) and EDA tools support for Intel's PDK (Process Development Kit) for external Foundry customers, we want you on our team.

About This Role

This role encompasses installation, maintenance, and technical support of design environment (automation scripts, front-end and back-end design tools, flows, processes, and licenses) as well as compute environment (storage, compute, netbatch, ION, etc.). You will also provide technical support for Intel PDK and collateral.

Key Responsibilities

• Resolve designer's tool / methodology issues on the path to TapeOut.
• Provide support for design ramp up through training / documentation.
• Interact with EDA providers and ensure required tools features are available for the projects with high quality.
• Closely partner with PDK/library experts, flow development teams, as well as with product design teams Collaborate with EC to provision adequate compute capacity and help debug any associated issues.
• Create automation (scripts, checkers, etc.) for installation of design environment (PDKs, EDA tools, licenses, etc.) to simplify and accelerate design processes.
• Support the integration of new tools and methods into existing design workflows, ensuring seamless adoption and scalability.
• Excellent communication, networking, presentation skills high-quality standards.

Qualifications

• Minimum Qualifications: US Citizenship required. Ability to obtain a US Government Security Clearance TS/SCI. BS in Electrical or Computer Engineering with 3+ years' experience or MS in Electrical or Computer Engineering with 2+ years' experience in front-end and back-end design tools and flows. Experience in EDA tools and methodologies, including debugging and problem-solving. Experience in physical design, optimization, and tools flows and methodology (TFM). Experience with Verilog/ VHDL - Tcl, Perl, Python scripting. Linux Experience: bash, tcsh.
• Preferred Qualifications: Active US Government Security Clearance with a minimum of Secret level. Hands-on experience of industry standard front-end and back-end EDA tool installs. Experience in installation of foundry PDK and flows (Cheetah, etc.) Experience with debugging and design automation.

Job Information

Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro

Equal-Opportunity Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Benefits and Compensation

Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $117,620.00-227,270.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

No Fees

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.