CPU SoC Verification Engineer

Socket.dev; San Diego (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google in San Diego is seeking a CPU SoC DV Engineer to ensure the functional integrity of CPU subsystems from RTL simulation through final silicon characterization. You will develop robust verification environments, drive GLS, and collaborate with ATE teams to debug and stabilize high-speed patterns in production.

Join a team that pushes boundaries in custom silicon solutions powering Google\'s direct-to-consumer products, delivering performance, efficiency, and seamless integration.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 4 years of experience with ARM-based SoC verification, including cache coherency, NoC interconnects, or high-speed bus protocols.
• Experience with post-silicon debug across PVT corners.
• Experience in RTL verification and GLS workflows.

Responsibilities

• Drive ARM SoC and sub-system level verification, simulation, and debug for CPU RTL and gate-level netlists.
• Lead post-silicon debug to diagnose hardware failures and ensure pattern stability in production.
• Translate simulation-based functional sequences into ATE/SLT-ready formats, ensuring high-fidelity pattern conversion through virtual tester environments.
• Execute GLS and timing-annotated (SDF) simulations using industry-standard EDA tools.
• Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation.

Skills

ARM-based SoC verification

NoC interconnects

GLS workflows

RTL verification

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Master's or PhD preferred (EE/CE/CS)

Tools

UVM/OVM

Python

Perl

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with ARM-based SoC verification, including cache coherency, Network-on-Chip (NoC) interconnects, or high-speed bus protocols.
• Experience with post-silicon debug and diagnosing failures across Process, Voltage, and Temperature (PVT) corners.
• Experience in RTL verification and Gate Level Simulation (GLS) workflows.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with UVM/OVM methodologies and using Python or Perl to automate ARM SoC verification flows.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a CPU SoC DV Engineer, you will be responsible for ensuring the functional integrity of CPU subsystems from initial RTL simulation through to final silicon characterization. You will develop robust verification environments, drive GLS, and partner with ATE teams to debug and stabilize high-speed patterns in a production environment.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

• Drive ARM SoC and sub-system level verification, simulation, and debug for CPU RTL and gate-level netlists.
• Lead post-silicon debug efforts to diagnose complex hardware failures and ensure pattern stability in production.
• Translate simulation-based functional sequences into ATE/SLT-ready formats, ensuring high-fidelity pattern conversion through virtual tester environments.
• Execute GLS and timing-annotated (SDF) simulations using industry-standard EDA tools.
• Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation.