CPU Core Design Verification Test Generator Lead

Tenstorrent; Fort Collins (CO); Hybrid; USD 150,000 - 200,000; Full time

Job summary

Tenstorrent in Fort Collins, CO is seeking a CPU Core Design Verification Test Generator Lead with 8+ years in CPU design verification. You will own test generator development for high-performance out-of-order RISC-V cores, shaping ISA and microarchitectural verification pre- and post-silicon.

The role is hybrid, based in Fort Collins, and you will lead a small team of 4-5 engineers while staying hands-on. The position offers a collaborative environment focused on cutting-edge AI hardware, with

Qualifications

• 8+ years in CPU design verification or closely related CPU validation work.
• Led development of test generators for x86, ARM, or RISC-V ISA environments.
• Understand CPU ISA behavior, privileged architecture, and high-performance out-of-order microarchitecture.
• Comfortable building tools, stimulus, and automation that scale verification across large CPU programs.
• Strong communication across design, DV, architecture, emulation, and post-silicon teams.

Responsibilities

• Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores.
• Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification in pre-silicon and post-silicon.
• Develop directed and randomized stimulus targeting architectural corner cases and complex CPU behavior.
• Support RISC-V certification work, including test content, compliance flows, debug, and closure.
• Guide a small team of 4-5 engineers while staying hands-on with implementation, debug, and verification execution.

Skills

CPU verification

Test generators

Team leadership

ISA knowledge

Automation tools

Job description

CPU Core Design Verification Test Generator Lead

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

At Tenstorrent, we build open, state of the art compute for real workloads and real developers.

You will own CPU focused test generator development and verification strategy, shaping how our out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior.

This role is hybrid, based out of Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You bring 8+ years in CPU design verification, test generation, or closely related CPU validation work.
• You have led development of test generators for x86, ARM, or RISC-V ISA environments.
• You understand CPU ISA behavior, privileged architecture, and high-performance out-of-order CPU microarchitecture.
• You are comfortable building tools, stimulus, and automation that scale verification across large CPU programs.
• You communicate clearly across design, DV, architecture, emulation, and post-silicon teams.

What We Need

• Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores.
• Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification in both pre-silicon and post-silicon
• Develop directed and randomized stimulus that targets architectural corner cases, instruction interactions, and complex CPU behavior.
• Support RISC-V certification work, including test content, compliance flows, debug, and closure.
• Guide a small team of 4-5 engineers while staying hands-on with implementation, debug, and verification execution.

What You Will Learn

• How Tenstorrent designs and validates high-performance RISC-V CPU cores and clusters.
• Techniques for scaling CPU test generator infrastructure across core, cluster, and chip-level environments.
• Ways to apply ISA-driven stimulus to complex CPU verification and debug workflows.
• How to scale coverage, debug, and generator methodology across multiple CPU programs within Tenstorrent’s broader compute roadmap.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Tenstorrent’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.