CPU Architecture- Physical Design Lead

Tenstorrent; United States; Remote; USD 100,000 - 500,000; Full time

Job summary

An innovative firm is on the lookout for a Senior Physical Design Engineer to join their dynamic team. This remote role focuses on high-speed CPU core design, where you will collaborate closely with architects to shape the future of CPU technology. You will be responsible for all aspects of the design flow, from feasibility analysis to design closure, utilizing industry-standard tools. The ideal candidate will possess strong communication and collaboration skills, and a robust background in integrated circuit design. If you're ready to make a significant impact in a forward-thinking environment, this opportunity is perfect for you.

Qualifications

• 10+ years of experience in relevant work in CPU core design.
• Strong experience in SOC/ASIC/GPU/CPU design flows.

Responsibilities

• Hands-on experience with design flow from feasibility to design closure.
• Develop better design methods for improved synthesis convergence.

Skills

High-speed CPU core design

Synthesis and place and route

Power and timing analysis

Excellent communication skills

Collaboration skills

Scripting (Python, TCL)

Education

Bachelor in Computer Engineering

Master in Computer Engineering

Tools

Synopsys

Cadence

Job description

We are seeking a highly skilled Senior Physical Design Engineer with expertise in high-speed CPU core design to join our team. This role will be working closely with our Architects to develop the next generation of CPU.

This role is remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Hands-on experience with synthesis and place and route using industry standard tools for next generation high speed CPU core design.
• Perform all aspects of design flow from feasibility analysis, logic synthesis, place and route, FEV, power, timing, quality checks, and design closure.
• Develop and recommend better design method practices to enable better synthesis convergence.
• Plan out resources, schedule, project PPA.
• The ideal candidate will exhibit behavioral traits that demonstrate:
• Willingness to work with others in a highly complex decision space.
• Skills at developing an implementation plan monitoring key indicators and communicating resource needs and scoping risk to deliver value on schedule.
• Excellent verbal and written communication and collaboration skills.

Experience & Qualifications:

• Bachelors in Computer Engineering or Electrical Engineering with 10+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering (or higher degree) with 10+ years of relevant work experience.
• Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure.
• PV convergence (including static timing and power analysis).
• Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools.
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows.
• Scripting in an interpreted language (Python, TCL).

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.