Chief Silicon Architect for XR & AI Systems

Google

San Jose (CA)

On-site

USD 236,000 - 329,000

Full time

4 days ago
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Job summary

Google's XR team is building the future of immersive computing. As Head of Silicon Systems and Architecture, you will define hardware foundations for the next-generation headsets and smart glasses, ensuring SoCs are tightly integrated with perception software and AI workloads.

This role leads a multi-disciplinary group of engineers, negotiates with external silicon providers, and shapes reference designs while advancing energy-efficient, low-latency experiences for users worldwide.

Qualifications

  • Bachelor's degree or higher in EE/CE or equivalent practical experience.
  • 8 years in silicon engineering, system integration, hardware design, or silicon architecture.
  • 5 years of technical leadership with direct reports.
  • Experience shipping consumer electronics to mass production.
  • Ability to align multiple engineering teams and external silicon providers.

Responsibilities

  • Define the multi-year silicon roadmap across APs, co-processors, and connectivity.
  • Lead deep-dives into CPUs, GPUs, ISPs, DSPs, NPUs and ensure AI workloads are silicon-optimized.
  • Architect split-compute topologies for XR glasses and companion devices.
  • Bridge Core Tech, Platform SW, HW NTI and external chipset vendors.
  • Mentor a team of system architects and explore new tech and architectures.

Skills

Technical leadership
Cross-team collaboration
Silicon architecture
XR/AR/VR experience
Hardware design

Education

Bachelor's degree in Electrical Engineering or Computer Engineering
Master's degree or PhD in Electrical Engineering or related field

Job description

Google's XR team is building the future of immersive computing. As Head of Silicon Systems and Architecture, you will define hardware foundations for the next-generation headsets and smart glasses, ensuring SoCs are tightly integrated with perception software and AI workloads.

This role leads a multi-disciplinary group of engineers, negotiates with external silicon providers, and shapes reference designs while advancing energy-efficient, low-latency experiences for users worldwide.

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