Chief Low-Latency Market Data Engineering

Two Sigma; New York (NY); Hybrid; USD 250,000 - 325,000; Full time

Benefits offered by this job

Medical & dental insurance

401k with company match

Life & disability insurance

Onsite gym

Tuition reimbursement

Generous time off

Hybrid work policy

Job summary

Two Sigma is seeking a senior leader to own the market data engineering function for its hedge fund and market-making businesses. You will define the multi-year roadmap, drive end-to-end architecture for ultra-low-latency data, and oversee global exchange connectivity, leveraging FPGA acceleration and time-series storage expertise.

The role requires building and mentoring a top-tier engineering team, with strong C++ performance focus and Python support for research interfaces.

Qualifications

• Experience leading market data or low-latency engineering teams.
• Expertise in C++ for performance-critical, low-latency systems and Python for research surfaces.
• Experience with exchange connectivity, feed handlers, and market data protocols.
• Knowledge of hardware-accelerated solutions (FPGA) and clock synchronization (PTP).

Responsibilities

• Define and own the multi-year roadmap for market data engineering, balancing latency, coverage, cost, and resilience.
• Own end-to-end architecture for tick data capture, normalization, and internal distribution.
• Oversee direct exchange and venue connectivity across global markets.
• Lead deep technical work on low-level tick data constructs and storage strategies across asset classes.
• Build, mentor, and retain a high-caliber engineering organization with strong C++ standards.

Skills

Leadership

C++ (latency)

Python

Exchange connectivity

FPGA hardware

Time-series storage

Job description

Two Sigma is seeking a senior leader to own the market data engineering function for its hedge fund and market-making businesses. You will define the multi-year roadmap, drive end-to-end architecture for ultra-low-latency data, and oversee global exchange connectivity, leveraging FPGA acceleration and time-series storage expertise.

The role requires building and mentoring a top-tier engineering team, with strong C++ performance focus and Python support for research interfaces.