ASIC Verification Engineer

Hewlett Packard Enterprise; Durham (NC); On-site; USD 120,000 - 180,000; Full time

Job summary

Hewlett Packard Enterprise Development LP seeks an experienced ASIC/SoC verification engineer to lead verification efforts for complex networking SoCs. You will own test plans, develop environments from scratch, and drive coverage closure across block, subsystem, and full-chip levels.

The role requires hands-on expertise in SystemVerilog, UVM, and modern verification methodologies, with exposure to emulation and post-silicon bring-up advantages.

Qualifications

• 4+ years in ASIC/SoC verification with test-plan ownership.
• Strong SystemVerilog and UVM experience.
• Understanding of randomization, constraints, functional coverage, and SVA.
• Hands-on test planning, coverage analysis, and debugging of complex SoCs.
• Familiar with coverage analytics, regression dashboards, and CI flows.
• Knowledge of low-power UPF or formal verification is a plus.
• Exposure to emulation environments and hardware acceleration is desirable.
• Experience with post-silicon bring-up and debug is beneficial.

Responsibilities

• Own and drive block-level to FullChip verification efforts from test plans to coverage closure.
• Develop verification environments from scratch and maintain test benches.
• Plan, execute, and optimize verification strategies for networking ASICs.
• Leverage simulation, emulation, and waveform debugging to verify design intent.
• Contribute to regression suites and CI integration for ongoing QA.

Skills

ASIC/SoC verification

SystemVerilog

UVM methodology

test planning

coverage analysis

debugging

emulation environments

waveform debugging

post-silicon bring-up

CI/regression dashboards

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

* 4+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.* Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.* Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).* Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.* Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.* Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.* Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.* Exposure to emulation environments, hardware acceleration, or traffic-model integration.* Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins).* Understanding of low-power (UPF) or formal verification methodologies.* Own and drive block-level/subsystem/FullChip verification efforts, from creating test plans to achieving comprehensive coverage closure* Experience with post-silicon bring-up and debug is a plus.* Familiarity with emulation environments and debug flows is desirable.HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: .Please ensure the resume you submit to us does not include any sensitive personal data. Sensitive personal data includes data revealing information about your racial or ethnic origin, political opinions, religious or philosophical beliefs, trade union membership, health, sex life or sexual orientation. To the extent the resume you submit does contain this type of personal data, you consent to the storing and processing of this data by HPE for the purpose of reviewing and managing your application.