ASIC Technical Program Manager

The Consensus; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Medical, dental, and vision

Housing subsidy for commuting

Relocation support to San Jose

Wellness benefits

Daily lunch and dinner in office

Unlimited compute budget

Job summary

Etched is seeking a highly skilled ASIC Technical Program Manager to join our silicon team. This hands-on role drives execution across the RTL-to-GDSII flow and oversees coordination between Physical Design, DFT, DV, and RTL, while managing external vendors and IP providers.

You will shepherd tape-out milestones and ECO cycles with urgency befitting a first-silicon program. The ideal candidate has real tape-out experience, strong cross-team collaboration skills, and the ability to communicate

Qualifications

• At least one full ASIC tape-out experience end-to-end.
• Solid understanding of RTL-to-GDSII flow and inter-team handoffs.
• 5+ years in technical/hardware program management or similar role.
• Experience with external EDA vendors or implementation partners.
• Excellent follow-through and proactive dependency management.

Responsibilities

• Own program management across Physical Design, DFT, DV, RTL, and Post-Silicon teams.
• Engage external vendors and hold them to timelines and deliverables.
• Identify risks, schedule slippage, and develop mitigation strategies.
• Plan and execute complex multi-team hardware programs and tape-outs.
• Provide regular updates to engineering leads and executives.
• Coordinate tooling and dashboards to improve engineering visibility.

Skills

ASIC tape-out

RTL-to-GDSII flow

Vendor management

Cross-functional coordination

Communication skills

Education

Bachelor's degree in Engineering, Computer Science, or related field

Tools

EDA tools

IP/implementation partners

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

Etched is seeking a highly skilled and motivated ASIC Technical Program Manager to join our silicon team. This is a hands-on, high-accountability role for someone who has lived inside the ASIC development cycle and can drive technical execution, not just track it. You will own program coordination across Physical Design, DFT, DV, and RTL teams while managing relationships with external vendors including IP providers, implementation partners, and EDA tool vendors. The ideal candidate has real tape-out experience, understands the full RTL-to-GDSII flow, and operates with the urgency and proactivity that a first-silicon program demands.

Key Responsibilities

• Cross-Functional Technical Coordination: Own program management across Physical Design, DFT, DV, RTL, and Post-Silicon teams. Understand inter-team dependencies - know who owns what, when handoffs need to happen, and what needs to be signed off before downstream work can begin (e.g., RTL version gates for synthesis, DFT insertion checkpoints, ECO cycles).

• Vendor Management: Engage directly with external vendors, including EDA partners and implementation partners. Hold vendors accountable to timelines and deliverables. Be prepared to push back, defend Etched’s technical requirements, and elevate when needed.

• Risk Identification and Mitigation: Proactively surface critical path risks, schedule slippage, and cross-team blockers. Develop mitigation strategies in partnership with engineering leads and elevate appropriately to technical and executive stakeholders.

• Project Planning and Execution: Manage the scheduling and execution of complex, multi-team hardware programs. Keep projects on track across tape-out milestones, synthesis respins, and signoff cycles.

• Stakeholder Communication: Provide regular, clear updates to engineering leads, VP-level stakeholders, and executive leadership on project status, risks, and decisions required. Set the tone for meetings, facilitate alignment, mediate technical disagreements, and drive to decisions.

• Process Coordination: Work with ops and engineering teams to maintain accurate tracking of program state, action owners, and open items. Support the adoption of tooling and dashboards that improve engineering visibility - though dashboard creation itself sits with the ops team.

• Technical Acumen: Bring enough ASIC domain knowledge to communicate credibly with engineers across the design stack and with external partners. You don’t need to be a designer, but you need to know the difference between a .3 and .5 RTL release, understand where DFT fits in the flow, and have a feel for what a synthesis restart actually involving.

You may be a good fit if you have (Must-have qualifications)

• At least one full ASIC tape-out under your belt. You should be able to speak fluently to what that process looks like end-to-end.

• Solid understanding of the RTL-to-GDSII flow, including where Physical Design, DFT, DV, and RTL teams intersect and hand off to each other.

• 5+ years of experience in technical program management, engineering program management, or a closely related role within the semiconductor or hardware space.

• Experience working directly with external EDA vendors or implementation partners - you’ve been in those rooms and know how to hold your ground.

• Exceptional follow-through and proactivity. You chase down dependencies; you don’t wait for them to surface.

• Strong communication and facilitation skills - you set a productive tone in meetings, keep discussions on track, and bring people to alignment.

• Comfort with fast-paced, ambiguous startup environments where priorities shift and programs evolve quickly.

• Bachelor’s degree in Engineering, Computer Science, or a related field.

Benefits

• Medical, dental, and vision packages with generous premium coverage

  • $500 per month credit for waiving medical benefits

• Housing subsidy of $2k per month for those living within walking distance of the office

• Relocation support for those moving to San Jose (Santana Row)

• Various wellness benefits covering fitness, mental health, and more

• Daily lunch and dinner in our office

• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.