ASIC Physical Design Engineer II (Full Time) - United States

Cisco; San Jose (CA); On-site; USD 126,000 - 203,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) with Cisco matching

Paid parental leave

Job summary

Cisco’s Silicon One team is seeking a Physical Design Engineer to lead RTL-to-GDSII implementation for cutting-edge Networking chips. You will optimize floor planning, timing, and backend flows while collaborating across RTL, DFT, and EDA teams to secure high-performance silicon.

The role requires expertise in ASIC physical design concepts, floor planning, clock and power distribution, and STA. Proficiency with Cadence Innovus, Synopsys tools, and scripting is highly valued.

Qualifications

• Qualifying education in ASIC Physical Design or related field.
• Strong knowledge of floor planning, clock tree synthesis, and power distribution.
• Experience with RTL-to-GDSII flows and timing closure.

Responsibilities

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
• Define and execute hierarchical floor planning, place and route, clock/power distribution, timing convergence.
• Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; develop scripts in STA tools.
• Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime.
• Collaborate with RTL, DFT, EDA vendors and tool owners to improve design efficiency.

Skills

RTL-to-GDSII implementation

Floor planning

Static timing analysis (STA)

Python scripting

Collaboration

Education

Master's degree in Electrical Engineering or related field

Bachelor's degree in Electrical Engineering or related field

Tools

Cadence Innovus

Synopsys ICC2

Synopsys Design Compiler

Mentor Calibre

PrimeTime

Job description

Meet the Team

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.

Our innovations in silicon, optics, and hardware platforms are shaping the technology industry.

We’re a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly.

Join us to power the future of the digital world.

Your Impact

As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips.

You will:

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
• Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime.
• Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.
• Evaluate and implement new timing methodologies; provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

Minimum Qualifications

Meet one of the following (completed within the past 3 years or expected to be completed within the next 12 months):

• A Master's degree with 0 years of work experience;
• A Bachelor's degree with 2 years of work experience.

Qualifying education and work experience should be in ASIC Physical Design, ASIC design, engineering or a related field.

Foundational knowledge of ASIC physical design and implementation flows gained through academic projects, internships, or relevant coursework.

Understanding of physical design concepts, including floor planning, clock tree synthesis, power distribution, and I/O planning.

Exposure to the physical design lifecycle, including logic synthesis, placement, routing, and basic timing closure.

Preferred Qualifications

Proficiency in scripting languages such as Python, Tcl, or Perl for task automation and data analysis.

Hands‑on experience with industry‑standard EDA tools (e.g., Cadence Innovus, Synopsys ICC2, or Synopsys Design Compiler) through lab work or internships.

Familiarity with physical verification processes (DRC/LVS) using tools such as Mentor Calibre or Synopsys ICV.

Exposure to static timing analysis concepts and tools, such as PrimeTime.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds.

These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless.

We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

• U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.
• Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
• U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non‑exempt employees 1 paid day off for employee’s birthday, paid year‑end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco.
• Non‑exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full‑time employees.
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations).
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next.
• Additional paid time away may be requested to deal with critical or emergency issues for family members.
• Optional 10 paid days per full calendar year to volunteer.
• For non‑sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
• Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non‑quota components, subject to the applicable Cisco plan.
• For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
• For non‑quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target.
• Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area: $125,700.00 - $203,100.00 Non-Metro New York state & Washington state: $111,700.00 - $180,800.00 *

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.