ASIC Physical Design Engineer

Cisco

San Jose (CA)

Presencial

USD 168.000 - 245.000

Jornada completa

hace 6 horas
Sé de los primeros/as/es en solicitar esta vacante
Generador de candidaturas

Una candidatura completa en un minuto — currículum y carta de presentación personalizados, listos para enviar.

Supera los filtros ATS

Descripción de la vacante

Cisco's Common Hardware Group in the U.S. seeks a senior Physical Design engineer to drive RTL‑to‑GDSII implementation for advanced silicon. You will optimize timing, power integrity, and die size while coordinating with RTL, EDA, and flow teams to ensure robust tapeouts.

Join a team delivering Cisco Silicon One architectures and collaborating across multiple technologies to push performance in data center and enterprise gear. The role is on-site in the United States.

Formación

  • BS / MS / PhD in Electrical Engineering with 2+ to 6+ years Physical Design experience required.
  • Experience with RTL2GDSII flow and design tapeouts in advanced nodes (7nm/5nm/3nm).
  • Proficiency with leading EDA tools (Innovus, Tempus/Primetime, Calibre).

Responsabilidades

  • RTL‑to‑GDSII implementation with floorplanning, place-and-route, and STA; optimize performance and die size.
  • Analyze tool flows and improve efficiency with incremental or transformational changes.
  • Collaborate with RTL, DFT, implementation, EDA vendors, and flow teams to enable best‑in‑class design methodology.
  • Lead clock tree synthesis strategies and provide feedback to implementation teams.
  • Perform STA setup, convergence, and sign‑off across multi‑mode/multi‑corner scenarios.
  • Complete Timing ECO implementation using Tweaker/Primetime based flows and contribute automation for STA.
  • Evaluate multiple timing methodologies/tools across technologies and design types.

Conocimientos

RTL2GDSII flow
Tapeouts 7nm/5nm/3nm
Python
TCL
Perl
Power integrity

Educación

Bachelor’s Degree in Electrical Engineering
Master’s Degree in Electrical Engineering
PhD in Electrical Engineering

Herramientas

Innovus
Tempus/Primetime
Redhawk/Voltus
Calibre

Descripción del empleo

The application window is expected to close on: 10/29/2026

Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top‑of‑rack switches to web‑scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry.

Your Impact
  • RTL‑to‑GDSII implementation, including hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks with a focus on performance and die size optimization.
  • Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
  • Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best‑in‑class design methodology.
  • Guide clock tree synthesis (CTS) strategies and provide actionable feedback to the implementation teams.
  • Execute STA setup, convergence methodologies, and sign‑off processes across multi‑mode, multi‑corner scenarios.
  • Complete Timing ECO implementation using Tweaker/Primetime‑based flows and contribute to automation for STA methodology.
  • Evaluate multiple timing methodologies/tools across different technologies and design types.
Minimum Qualifications
  • Bachelor’s Degree in Electrical Engineering with 6+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 4+ years of Physical Design experience, or PhD in Electrical Engineering with 2+ years of Physical Design experience.
  • Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies.
  • Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre.
Preferred Qualifications
  • Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
  • Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
  • Experience with Python, TCL, or Perl programming.
Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
  • 1 paid day off for employee’s birthday, paid year‑end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
  • Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full‑time employees
  • Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
  • 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
  • Additional paid time away may be requested to deal with critical or emergency issues for family members
  • Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees On Sales Plans Earn Performance‑based Incentive Pay On Top Of Their Base Salary, Which Is Split Between Quota And Non‑quota Components, Subject To The Applicable Cisco Plan. For Quota‑based Incentive Pay, Cisco Typically Pays As Follows
  • .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
  • 1.5% of incentive target for each 1% of attainment between 50% and 75%;
  • 1% of incentive target for each 1% of attainment between 75% and 100%; and
  • Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non‑quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area

$155,000.00 - $256,000.00

Non-Metro New York State & Washington State

$138,100.00 - $227,900.00

  • For quota‑based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
  • Employees in Illinois, whether exempt or non‑exempt, will participate in a unique time off program to meet local requirements.
Consigue la evaluación confidencial y gratuita de tu currículum.

o arrastra y suelta tu archivo aquí

Similar jobs

Puestos de trabajo similares que vale la pena comparar

ASIC Physical Design Engineer
ASIC Physical Design Engineer

Cisco • Austin (TX)

Presencial
USD 168.000 - 245.000
ASIC Physical Design Engineer
ASIC Physical Design Engineer

Cisco Systems, Inc • San Jose (CA)

Presencial
USD 170.000 - 250.000
ASIC Physical Design Engineer II (Full Time) - United States
ASIC Physical Design Engineer II (Full Time) - United States

Cisco Systems, Inc • San Jose (CA)

Presencial
USD 150.000 - 230.000
ASIC Physical Design Engineer II (Full Time) - United States
ASIC Physical Design Engineer II (Full Time) - United States

Cisco • San Jose (CA)

Presencial
USD 126.000 - 203.000
Medical, dental and vision insurance
401(k) with Cisco matching
Paid parental leave
ASIC Physical Design Engineer II (Full Time) - United States
ASIC Physical Design Engineer II (Full Time) - United States

Cisco Systems, Inc. • San Jose (CA)

Presencial
USD 150.000 - 230.000
Medical, dental & vision insurance
401(k) with company match
Paid parental leave
+4
Physical Design Engineer I (Co-op) - United States
Physical Design Engineer I (Co-op) - United States

Cisco Systems, Inc. • Maynard (MA)

Presencial
USD 44.000 - 185.000
Physical Design Engineer I Coop United States
Physical Design Engineer I Coop United States

Cisco • Maynard (MA)

Presencial
USD 18.000 - 30.000
Senior ASIC Design Engineer
Senior ASIC Design Engineer

Cisco Systems, Inc. • San Jose (CA)

Presencial
USD 168.000 - 245.000
Physical Design Engineer I (Co-op) - United States
Physical Design Engineer I (Co-op) - United States

Cisco Systems, Inc • Maynard (MA)

Presencial
USD 20.000 - 40.000
Benefit from Cisco intern program
Hardware Engineer
Hardware Engineer

Cisco • Milpitas (CA)

Presencial
USD 138.000 - 197.000