ASIC Implementation Engineer STA

Broadcom; San Jose (CA); On-site; USD 143,800 - 230,000; Full time

Benefits offered by this job

Discretionary annual bonus

Annual equity awards

comprehensive benefits package

Job summary

Broadcom in San Jose, CA is seeking a Full Chip STA Engineer to own timing closure for ASIC across PVT corners, developing constraints and sign-off strategies. You will drive MMMC analysis, ECOs, and power/performance tradeoffs with RTL, PD, and DFT teams.

The role requires 12+ years of ASIC STA experience, expertise with Cadence/Synopsys sign-off tools, and strong scripting ( TCL, Python, Perl). Competitive salary and equity accompany Broadcom's comprehensive benefits.

Qualifications

• Bachelor’s degree in Electrical Engineering or Computer Engineering.
• 12+ years hands-on ASIC STA and timing constraints development with Cadence or Synopsys tools.
• Experience driving timing closure by effectively managing on‑chip variation derates and multi‑corner constraints.
• Proficient in TCL and Python, PERL, or Shell scripting.
• Strong problem solving skills with attention to technical details.
• Be a strong team player with clear and precise communication.
• EDA Tool Expertise: Expert proficiency in industry‑standard sign‑off tools.

Responsibilities

• Own final timing closure for ASIC across all process, voltage, and temperature corners.
• Author, validate, and maintain SDC for various modes including functional and test modes (Scan, MBIST, ATPG).
• Incorporate sign-off corners, margins, and derates into timing analysis flows and methodologies.
• Deep knowledge of On-Chip Variation (AOCV/POCV), Signal Integrity (crosstalk), and IR-drop aware STA.
• Manage MMMC analysis across hundreds of timing scenarios for reliability.
• Automate, generate and implement ECOs to fix setup, hold, and transition violations.
• High proficiency in Tcl (primary for EDA tools), Python, and Perl for automation.
• Collaborate with RTL, Physical Design, and DFT teams to resolve timing issues.
• Balance power/performance/area tradeoffs in chip implementation flows.
• Document best practices to drive continuous improvements on future projects.

Skills

Strong problem solving

Clear communication

Team player

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Tools

Cadence tools

Synopsys tools

TCL scripting

Python scripting

Perl scripting

Job description

The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions.

Key Responsibilities

• Full-Chip Timing Sign-off: Own the final timing closure for ASIC, performing quality checks across all process, voltage, and temperature (PVT) corners
• Constraint Development: Author, validate, and maintain SDC for various modes, including functional and test modes (Scan, MBIST, ATPG)
• Analyze foundry guidelines and work with the team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies
• Advanced Timing Concepts: Deep knowledge of On-Chip Variation (AOCV/POCV), Signal Integrity (crosstalk), and IR-drop aware STA
• Multi-Mode Multi-Corner (MMMC) Analysis: Manage and analyze hundreds of timing scenarios to ensure reliability across diverse operating environments
• Timing ECOs: Automate, generate and implement ECOs to fix setup, hold, and transition violations in the design cycle
• Scripting: High proficiency in Tcl (primary for EDA tools), Python, and Perl for automating analysis flows and data mining.
• Cross-Functional Collaboration: Partner with RTL, Physical Design, and DFT teams to resolve complex timing issues and define guard-banding requirements
• Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows
• Document best practices and lessons learned to drive continuous improvements in future projects

Qualifications

• Bachelor’s degree in Electrical Engineering or Computer Engineering
• A minimum of 12 years of hands‑on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools
• Experience in driving timing closure by effectively managing on‑chip variation derates, optimizing multi‑mode multi‑corner constraints
• Well versed with scripting languages like TCL and Python, PERL, or Shell
• Strong problem solving skills with attention to every technical aspect
• Be a strong team player with clear and precise communication skills
• EDA Tool Expertise: Expert proficiency in industry‑standard sign‑off tool

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 to USD 230,000.00.

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Equal Opportunity Employer

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.