ASIC Engineering Technical Leader - SDC

Cisco Systems, Inc.; California, San Jose (MO, CA); On-site; USD 95,000 - 140,000; Full time

Job summary

An established industry player is seeking a diligent Design/SDC Engineer to join their innovative ASIC team. This role offers the opportunity to work on cutting-edge silicon architecture for web-scale networks, collaborating with talented engineers to refine design and timing constraints. You will be instrumental in ensuring seamless physical design closure and contribute to the development of next-generation networking chips. The company fosters a culture of diversity and inclusion, providing a supportive environment for professional growth and community engagement. If you are passionate about technology and eager to make an impact, this is the perfect opportunity for you.

Benefits

Onsite gym

Healthcare

Cafeteria

Social interest groups

Philanthropy opportunities

Qualifications

• 8+ years of ASIC experience with strong analytical skills.
• Proficient in SDC/STA tools and scripting for automation.

Responsibilities

• Oversee full-chip SDCs and collaborate with Physical Design teams.
• Develop methodologies to integrate full-chip SDC changes.

Skills

SDC development

Static Timing Analysis

Verilog/SystemVerilog programming

Digital design concepts

Scripting languages (Python, Perl, TCL)

Education

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

Tools

PrimeTime

Tempus

Synopsys DC/DCG/FC

Spyglass CDC

Synopsys Formality

Cadence LEC

Job description

Application Deadline

The application window is expected to close on: May 9, 2025. Job postings may be removed earlier if the position is filled or a sufficient number of applications are received.

Onsite Requirement

This role requires being onsite in San Jose, CA, 4+ days/week.

Meet the Team

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team offers a unique experience for ASIC engineers by combining resources from a large multi-geography organization and a large campus with amenities like an onsite gym, healthcare, cafe, social interest groups, and philanthropy, with the startup culture and growth opportunities of a smaller ASIC team.

You will work with exceptional talent experienced in ASIC design and development, and collaborate with other ASIC teams from concept to first customer shipments.

Your Impact

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will work with Front-end and Back-end teams to understand chip architecture and refine design and timing constraints for seamless physical design closure, contributing to next-generation networking chips.

Responsibilities include:

• Oversee full-chip SDCs and collaborate with Physical Design and DFT teams to close full-chip timing in multiple modes.
• Develop efficient methodologies to promote block-level SDCs to full-chip and integrate full-chip SDC changes back to block level.
• Ensure correctness and quality of SDCs early in the design cycle through methodology development and application.
• Review block-level SDCs and clocking diagrams, mentoring RTL design owners on SDC development.
• Create full-chip clocking diagrams and related documentation.
• Potentially engage in block-level RTL design or IP integration at the block or top level.

Minimum Qualifications:

• Bachelor's Degree in Electrical or Computer Engineering with 8+ years of ASIC or related experience, or Master's Degree with 6+ years.
• Experience with block/full-chip SDC development in functional and test modes.
• Experience with Static Timing Analysis and tools like PrimeTime/Tempus.
• Knowledge of digital design concepts such as clocking and asynchronous boundaries.
• Experience with synthesis tools (e.g., Synopsys DC/DCG/FC) and Verilog/SystemVerilog programming.

Preferred Qualifications:

• Experience with constraint analysis tools like TCM and CCD.
• Experience with Spyglass CDC and glitch analysis.
• Experience with Formal Verification tools like Synopsys Formality and Cadence LEC.
• Proficiency in scripting languages such as Python, Perl, or TCL.

#WeAreCisco

We celebrate diversity and foster an inclusive environment. Our culture encourages learning, development, and hybrid work. We support community engagement through employee resource organizations and volunteer opportunities. Our mission is to power an inclusive future for all through innovative technology and dedicated people. Join us and be your authentic self!