ASIC Engineer, Performance Architecture and Modeling

Meta; Nashville (TN); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization seeks an ASIC Engineer specializing in performance architecture and modeling to lead architectural performance analysis and pre-silicon modeling for custom infrastructure ASICs powering Meta’s AI and data center workloads.

You will drive modeling methodology, supervise microarchitectural exploration, and work with architecture, RTL, and software teams to ensure silicon meets throughput, latency, and efficiency targets at hyperscale.

Qualifications

• Bachelor's degree or equivalent practical experience in CS/CE or related field.
• 8+ years of ASIC design, silicon engineering, or related field.
• 5+ years in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation.
• Proficiency in C++ and Python for modeling, automation, and analysis.
• Experience with cycle-accurate or transaction-level models using C++/SystemC.

Responsibilities

• Define and own performance modeling strategy for custom infrastructure ASICs.
• Drive microarchitectural exploration across compute, memory, interconnect, and I/O to inform silicon decisions.
• Develop and validate pre-silicon models predicting post-silicon behavior for data-center workloads.
• Create workloads/kernels for ML training and inference.
• Establish benchmarking frameworks and bottleneck identification across the ASIC pipeline.
• Collaborate with architecture/RTL/physical teams to translate requirements.
• Work with software/systems teams to optimize workload scheduling and firmware against silicon perf.
• Lead cross-functional reviews and communicate results to leadership.
• Define long-term performance modeling roadmaps, tooling, automation, and sims platform investments.
• Mentor engineers in modeling techniques and analysis practices.
• Identify and resolve gaps between modeled and measured silicon behavior.

Skills

C++

Python

Assembly language

Compiler technologies

Education

Bachelor's degree in Computer Science/Engineering or equivalent

Tools

SystemC

SystemVerilog

VHDL

Job description

Summary:

Meta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads at scale. As an ASIC Engineer specializing in performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure. In this role, you will establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with architecture, design, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale.

Required Skills:

ASIC Engineer, Performance Architecture and Modeling Responsibilities:

1. Define and own the performance modeling strategy for custom infrastructure ASICs, including development of cycle-accurate and transaction-level simulation environments
2. Drive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O domains to inform silicon architecture decisions
3. Develop and validate pre-silicon performance models that accurately predict post-silicon behavior for data center workloads
4. Develop low-level workloads and kernels for machine learning training and inference applications
5. Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques across the full ASIC pipeline
6. Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into implementable microarchitectural specifications
7. Partner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior against silicon performance characteristics
8. Lead cross-functional technical reviews and communicate performance modeling results and architectural recommendations to engineering leadership
9. Define long-term performance modeling infrastructure roadmaps, including tooling, automation, and simulation platform investments
10. Mentor other engineers on performance modeling techniques, simulation methodology, and microarchitectural analysis best practices
11. Identify and resolve performance gaps between modeled and measured silicon behavior through structured root-cause analysis and model calibration

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2. 8+ years of experience in ASIC design, silicon engineering, or a related technical field
3. 5+ years of experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs
4. Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools
5. Experience developing cycle-accurate or transaction-level performance models using C++ and SystemC for complex digital systems including processors, memory subsystems, or high-speed interconnects
6. Experience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon
7. Experience defining microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams
8. Experience with assembly programming languages, and compiler technologies

Preferred Qualifications:

1. Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows
2. Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs
3. Familiarity with post-silicon performance validation and model-to-hardware correlation methodologies
4. Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis
5. Experience with GPU, machine learning, multi-threaded programming paradigm
6. Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimization

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affidative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].