ASIC DFT Technical Leader

Cisco Systems, Inc.; San Jose (CA); On-site; USD 210,600 - 305,100; Full time

Job summary

Cisco Systems, Inc. in San Jose, CA is seeking an ASIC implementation engineer to drive DFT/DFx and quality processes across the early product life cycle, from architecture through RTL implementation and post-silicon validation.

You will lead DFT strategy, collaborate across teams on test methodologies, and guide a team of engineers to deliver robust DFT/DFx solutions for next-generation networking chips.

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering required.
• 10+ years of ASIC hardware development experience.
• Experience with RTL QA checks, lint & CDC.

Responsibilities

• Develop comprehensive DFT/DFx solutions and architectures to support ATE screening, in-system test, debug and diagnostics.
• Lead RTL implementation from architecture specs and ensure RTL quality checks are met.
• Collaborate on innovative hardware DFT and test strategy for new silicon device models and stacked die, developing reusable test and debug methodologies and standards.
• Identify DFT challenges, brainstorm cross-functional solutions, and lead a team to deliver implementations on schedule.

Skills

DFT/DFx

RTL implementation

JTAG & BIST

Post-silicon test

Lint & CDC

Test & quality processes

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

JTAG

Scan architectures

Memory BIST

Job description

Meet the Team:

You will be part of the Silicon One development organization as an ASIC implementation engineer in San Jose, CA. As a member of this team you will be involved in crafting cutting edge next generation networking chips.

Your Impact:

You will be the lead to drive the DFT/DFx and quality process through the early product life cycle: the architecture definitions, RTL implementation and quality checks. You will also be engaged in relevant development of flow/methodologies, test plans, tape-out sign-off requirements, post silicon validation, production yield & DPPM support.

Key Responsibilities:

• Responsible for development of the comprehensive Design-for-Test (DFT) & DFx solutions and architectures that support ATE screening, in-system test, debug and diagnostics needs of the design.
• Lead the RTL implementation from the architecture specifications and required RTL quality checks implementations.
• Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re‑usable test and debug methodologies and standards.
• Work with the team on DFT challenge identification, cross‑functional solution brainstorming and implementation plan development, and lead a team of engineers to deliver expected implementations on schedule.

Minimum Qualifications:

• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 10+ years of ASIC Hardware Development experience.
• Prior experience on hardware design specifications and verification plan/matrix, RTL & testbench implementations.
• Prior experience on Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Post‑silicon test bring up and debug experience; Ability to analyze and root cause test failures on silicon.
• Prior experience on RTL QA checks, including lint & CDC

Preferred Qualifications:

• Scripting skills: Tcl, Python/Perl.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $210,600.00 to $305,100.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate’s hiring location, market conditions, job‑related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

• 10 paid holidays per full calendar year, plus 1 floating holiday for non‑exempt employees
• 1 paid day off for employee’s birthday, paid year‑end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non‑exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full‑time employees
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer

For non‑sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance‑based incentive pay on top of their base salary, which is split between quota and non‑quota components, subject to the applicable Cisco plan. For quota‑based incentive pay, Cisco typically pays as follows:

• .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
• 1.5% of incentive target for each 1% of attainment between 50% and 75%;
• 1% of incentive target for each 1% of attainment between 75% and 100%; and
• Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non‑quota‑based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:
$210,600.00 - $350,800.00

Non‑Metro New York state & Washington state:
$189,300.00 - $312,200.00

* For quota‑based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non‑exempt, will participate in a unique time off program to meet local requirements.