ASIC DFT STA Engineer

Cisco Systems, Inc.; San Jose (CA); On-site; USD 165,000 - 241,400; Full time

Benefits offered by this job

Medical, dental, and vision insurance

401(k) plan with matching contribution

Paid parental leave

Flexible vacation policy

Job summary

Cisco Systems, Inc. is seeking an ASIC DFT STA Engineer in San Jose, California. This role involves collaborating with teams to develop and validate timing constraints, driving the DFT process through implementation.

Ideal candidates should possess a strong background in timing constraints, FPGA design, and scripting. The position offers a competitive salary range between $165,000 to $241,400 annually, reflecting the value of skilled professionals in today’s AI-driven tech environment.

Qualifications

• Bachelors + 7 years, Masters + 4 years, or PhD + 1 year of related experience.
• Experience with RTL design, CDC/RDC, and conformal verification.
• Understanding of timing constraints and verification.

Responsibilities

• Develop timing constraints at various levels in test modes.
• Perform quality checks on timing constraints.
• Develop methodologies to streamline STA work.

Skills

Timing constraint development

RTL design experience

Scripting (Perl, TCL, Python)

Debugging and analyzing PCIE timing

Education

Bachelor's degree or higher

Tools

Synopsys TCM/Primetime

Synopsys Fusion Compiler

Tessent tools

Job description

The application window is expected to close on: 08/25/2026

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate with cross-functional teams, communicate complex timing data clearly. As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Key Responsibilities

• Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs.
• Check timing for unconstrained endpoints, no clock, etc.
• Your role may include SDC validation, CDC check, and SDC flow development.
• Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.

Minimum Qualifications

• Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience.
• Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development.
• Prior working experience in timing constraint development and verification.
• Prior programming experience with at least 2 or more of the following scripting languages: Perl, TCL, Python, or Makefile.

Preferred Qualifications

• Masters degree + 10 years of relevant experience.
• Prior working experience in debugging and analyzing PCIE timing constraints, TSMC memory timing constraints.
• Prior working experience in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.
• Prior working experience with SDC debugging & STA tools like Synopsys TCM/Primetime.
• Prior working experience with synthesis tools: Synopsys Fusion/design Compiler.
• Prior working experience with Tessent tool like DFT insertion in RTL.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $165,000.00 to $241,400.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

• .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
• 1.5% of incentive target for each 1% of attainment between 50% and 75%;
• 1% of incentive target for each 1% of attainment between 75% and 100%; and
• Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$165,000.00 - $277,600.00

Non-Metro New York state & Washington state:

$146,700.00 - $247,000.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.