ASIC DESIGN FOR TEST ENGINEER - Acacia

Cisco Systems, Inc.; San Jose (CA); Hybrid; USD 120,000 - 160,000; Full time

Job summary

An established industry player is seeking a talented ASIC Design Engineer to join their innovative ASIC team. In this role, you will be responsible for setting up and implementing various Design For Test methodologies, working closely with experienced engineers to ensure successful tape-out. This position offers the opportunity to collaborate with cross-functional teams and utilize advanced tools to drive efficiency and quality in ASIC design. Join a community that values diversity and fosters growth, where your contributions will help shape the future of technology and empower an inclusive environment.

Benefits

Hybrid work environment

Learning and development opportunities

Employee resource groups

Dedicated volunteer time

Qualifications

• 7+ years of experience in ASIC DFT flows and implementation.
• Experience with hierarchical ATPG and core wrapping techniques.

Responsibilities

• Implement and verify Design For Test with seasoned engineers.
• Collaborate with RTL/PD/STA/ATE teams for successful tape-out.

Skills

ASIC DFT flows

RTL implementation

ATPG

Synopsys/Mentor DFT tools

TCL scripting

Education

Bachelor's degree in relevant field

Master's degree in relevant field

PhD in relevant field

Tools

Synopsys DFT tools

Mentor DFT tools

Job description

Application Deadline

The application window is expected to close on 4/30/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team

Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G, and 1T bit speed fiber optic transmission market deployed in data centers, metro, long-haul, and ultra-long haul telecommunication networks. This role is within our ASIC team, specifically as part of the Design for Test group.

Your Impact

As a member of Acacia's ASIC team, you will set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC, and SCAN at chip and/or block level. You will also set up pattern generation flow for Scan/ATPG & MBIST/Repair/Fuse.

• You will work with seasoned DFT engineers to implement and verify Design For Test.
• You will interact with RTL/PD/STA/ATE teams, collaborating for successful tape-out.

Minimum Qualifications

• Typically: Bachelors + 7 years of related experience, or Masters + 4 years, or PhD + 1 year in ASIC DFT flows and implementation.
• Prior experience implementing scan control logic in RTL.
• Experience with hierarchical ATPG, core wrapping techniques, ATPG, and post-silicon DVT.
• Experience with Synopsys/Mentor DFT tools.

Preferred Qualifications

• Experience with scan compression and scan partitioning.
• Experience with MemoryBIST, eFuse, Repair, and yield improvement techniques.
• Experience with JTAG Boundary Scan insertion (AC/DC).
• Experience with clocking architecture during various ATPG modes such as: In-test and In-test.
• TCL scripting experience to automate DFT flows.

#WeAreCisco

#WeAreCisco is a community where every individual brings unique skills and perspectives to power an inclusive future. We celebrate diverse backgrounds and focus on unlocking potential. Our culture supports hybrid work, learning, and development at every stage. We foster communities through our employee resource groups, dedicated volunteer time, and initiatives aimed at inclusion and belonging.

Our purpose, driven by our people, makes us the leader in technology that powers the internet. We help customers reimagine applications, secure enterprises, transform infrastructure, and meet sustainability goals. Join us and be your authentic self!