ASIC Design Engineer - Design & Timing Constraints

Cisco Systems; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Join a dynamic front-end design team at a leading tech company, where you'll innovate in chip design and validation. As an ASIC engineer, you'll work on cutting-edge networking chips, collaborating with top-tier teams to refine designs and ensure timing accuracy. This role offers the chance to leverage the latest technologies and methodologies, making a significant impact in the industry. Be part of a culture that values diversity, learning, and community involvement, and help shape the future of technology while enjoying a supportive and inclusive work environment.

Benefits

Dedicated paid time off to volunteer

Employee resource organizations

Hybrid work options

Learning and development opportunities

Qualifications

• 8+ years of ASIC experience or 6+ years with a Master's degree.
• Proficient in Static Timing Analysis and SDC development.
• Strong understanding of digital design concepts.

Responsibilities

• Oversee fullchip SDCs and collaborate with design teams.
• Develop methodologies for timing closure and SDC correctness.
• Create fullchip clocking diagrams and documentation.

Skills

ASIC Design

Static Timing Analysis

Verilog/System Verilog

Scripting (Python, Perl, TCL)

Clocking and Async Boundaries

Education

Bachelor’s Degree in Electrical or Computer Engineering

Master’s Degree in Electrical or Computer Engineering

Tools

PrimeTime

Tempus

Synopsys DC/DCG/FC

TCM (Timing Constraint Manager)

Spyglass CDC

Synopsys Formality

Cadence LEC

Job description

The application window is expected to close on: 05/02/2025.

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team

Join our dynamic front-end design team at Cisco Silicon One, where innovation meets cutting-edge technology! As part of the heart of silicon development at Cisco, you'll engage in every facet of chip design, from architecture to validation, using the latest silicon technologies to create groundbreaking devices. Cisco Silicon One is the only unified silicon architecture that empowers customers to deploy top-tier silicon across diverse applications, from top-of-rack switches to expansive data centers. Be a part of shaping Cisco's revolutionary solutions by designing and testing advanced ASICs that integrate networking, compute, and storage into a single system. With tightly integrated hardware and software solutions, you'll gain exposure to all aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a significant impact in the industry. Join us and push the boundaries of what's possible!

Your Impact

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips.

Responsibilities include:

• Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
• Creating fullchip clocking diagrams and related documentation.

Minimum Qualifications

• Bachelor’s Degree in Electrical or Computer Engineering with 8+ years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 6+ years of ASIC or related experience
• Experience with block/full chip SDC development in functional and test modes.
• Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
• Understanding of related digital design concepts (eg. clocking and async boundaries)
• Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming

Preferred Qualifications

• Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
• Experience with Spyglass CDC and glitch analysis
• Experience using Formal Verification: Synopsys Formality and Cadence LEC.
• Experience with scripting languages such as Python, Perl, or TCL

#WeAreCisco

#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.

Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.

We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do!

Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!