ASIC Design Engineer - Design & Timing Constraints

Cisco Systems, Inc.; California, San Jose (MO, CA); On-site; USD 100,000 - 140,000; Full time

Job summary

Join a forward-thinking company as an ASIC Engineer, where you will engage in cutting-edge chip design and validation. This role involves collaborating with teams to refine design constraints and ensure the quality of SDCs. You'll work with the latest technologies to develop next-generation networking chips, pushing the boundaries of what's possible in silicon development. With a strong emphasis on innovation and teamwork, this position offers a unique opportunity to make a significant impact in the industry while fostering a culture of diversity and inclusion.

Benefits

Hybrid work environment

Diversity and inclusion programs

Learning and development opportunities

Volunteer opportunities

Qualifications

• 8+ years of ASIC experience or 6+ years with a Master's degree.
• Proficient in Static Timing Analysis and SDC development.

Responsibilities

• Oversee full-chip SDCs and collaborate with design teams.
• Develop methodologies for block-level SDCs to full-chip integration.

Skills

ASIC Design

Static Timing Analysis

Scripting (Python, Perl, TCL)

Digital Design Concepts

Education

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

Tools

PrimeTime

Tempus

Synopsys DC

Cadence LEC

Spyglass CDC

Job description

The application window is expected to close on: 05/02/2025.

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team

Join our dynamic front-end design team at Cisco Silicon One, where innovation meets cutting-edge technology! As part of the heart of silicon development at Cisco, you'll engage in every facet of chip design, from architecture to validation, using the latest silicon technologies to create groundbreaking devices. Cisco Silicon One is the only unified silicon architecture that empowers customers to deploy top-tier silicon across diverse applications, from top-of-rack switches to expansive data centers. Be a part of shaping Cisco's revolutionary solutions by designing and testing advanced ASICs that integrate networking, compute, and storage into a single system. With tightly integrated hardware and software solutions, you'll gain exposure to all aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a significant impact in the industry. Join us and push the boundaries of what's possible!

Your Impact

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you'll contribute to developing next-generation networking chips.

Responsibilities include:

• Oversee full-chip SDCs and work with physical design and DFT teams to close full-chip timing in multiple modes.
• Optionally, do block-level RTL design or block/top-level IP integration.
• Develop methodologies to promote block-level SDCs to full-chip and incorporate full-chip SDC changes back to block level.
• Ensure correctness and quality of SDCs early in the design cycle.
• Review block-level SDCs and clocking diagrams; mentor RTL design owners on SDC development.
• Create full-chip clocking diagrams and documentation.

Minimum Qualifications

• Bachelor's Degree in Electrical or Computer Engineering with 8+ years of ASIC or related experience or Master's Degree with 6+ years of experience.
• Experience with block/full-chip SDC development in functional and test modes.
• Experience with Static Timing Analysis and STA tools like PrimeTime/Tempus.
• Understanding of digital design concepts such as clocking and asynchronous boundaries.
• Experience with synthesis tools (e.g., Synopsys DC, FC), and Verilog/SystemVerilog programming.

Preferred Qualifications

• Experience with constraint analysis tools like TCM and CCD.
• Experience with Spyglass CDC and glitch analysis.
• Experience with Formal Verification tools like Synopsys Formality and Cadence LEC.
• Proficiency in scripting languages such as Python, Perl, or TCL.

#WeAreCisco

#WeAreCisco is a celebration of diversity, innovation, and inclusion, where every individual brings unique skills and perspectives to power an inclusive future for all. We foster a culture of learning, development, and hybrid work, supporting our employees' growth at every stage. Our commitment to community and belonging is reflected in our inclusive resource organizations, volunteer opportunities, and our purpose-driven mission to lead in technology that powers the internet. Join us and be your authentic self, making a difference with Cisco.