ASIC Design Engineer 2

Hewlett Packard Enterprise Company; Sunnyvale (CA); On-site; USD 106,000 - 214,000; Full time

Job summary

Hewlett Packard Enterprise seeks an ASIC Design Engineer 2 in California for an onsite role within the Juniper Silicon group. You will help design high-speed networking chips, from specifications to netlist, focusing on SystemVerilog RTL and timing closures with guidance from senior engineers.

Join a startup-like culture within a large company, with opportunities to grow your skills in a fast-paced, collaborative team and contribute to world-class silicon projects.

Qualifications

• Bachelor's degree in Electrical Engineering required; Master's strongly desired.
• Strong analytical and problem‑solving skills.
• Completed coursework in digital logic design.
• Strong coding skills in Verilog/SystemVerilog from coursework or internships.
• Knowledge of computer architecture / networking or ML is a plus.
• Excellent written and verbal communication skills are desirable.
• Knowledge of Perl or Python is a plus.

Responsibilities

• Start with a functional specification and develop a detailed micro-architecture with guidance from senior engineers.
• RTL coding with SystemVerilog (coding to synthesis).
• Write functional coverage/SVA; learn as needed.
• Timing closure work with PD to identify paths and fix RTL timing.
• Debug issues in block flagged by the verification team.
• Use state-of-the-art EDA tools for design checks.

Skills

Strong analytical

Verilog/SystemVerilog

Python/Perl

Good communication

Education

Bachelor's degree in Electrical Engineering

Master's degree preferred

Job description

ASIC Design Engineer 2

This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world. Our culture thrives on finding new and better ways to accelerate what's next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description:

ASIC Design Engineer 2

Organization:

HPE is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At Juniper Silicon group, we push the boundaries of what is possible in a piece of silicon die . We build cutting edge networking chips used to build world-class routers and switches.

Bring your passion and there are no boundaries to what you can accomplish here. We are like a start -up in a big company. Year after year, our group builds the most powerful and highest density networking chips.

As part of our fast-paced chip design group, you will become an expert in building high-speed ASICs, from specifications to final netlist. You can pick and choose where you want to work on - design/ verification or timing closure/PD. As you are getting started in you r career, w e will let you explore your passions here.

Open communications, empowerment, innovation, teamwork and customer success are the foundations of team culture . Thus, you set your own limits for learning, achievements and rewards.

Responsibilities:

• You will start with a functional specification of a module and come up with a detailed micro-architecture specification - do not worry, you will have guidance from our senior engineers on how to go about this if you have not done this before.
• RTL coding - we prefer you know System Verilog and have done several school/intern projects (coding to synthesis) using this language.
• W rite functional coverage/SVA (we will teach you how to do this if you haven't done this before)
• Timing closure - work with PD to identify timing paths and fix timing in RTL to meet the frequency target.
• Debug issues in your block found by v erification team.
• Use state-of-the-art EDA tools for various design checks.

Recommended skills

• Bachelor's degree in Electrical Engineering required, Master's strongly desired .
• Strong analytical/ problem solving skills.
• Should have taken courses for credit in digital logic design.
• Strong coding skills in Verilog/System Verilog through courses and intern projects
• Knowledge of Computer Architecture/networking protocols/machine learning through graduate level courses is a plus.
• Excellent written and verbal communications skills is good to have.
• Knowledge of Perl/Python is a plus

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

What We Can Offer You:

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Let's Stay Connected:

Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.

Job:

Engineering

Job Level:

TCP_02

\"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 105,500 - 213,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered.\"

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.