ASIC Design Engineer 2

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 106,000 - 214,000; Full time

Benefits offered by this job

Health & Wellbeing

Personal & Professional Development

Unconditional Inclusion

Job summary

Hewlett Packard Enterprise in Sunnyvale, California, is seeking an ASIC Design Engineer 2 to join our fast-paced chip design group. This onsite role focuses on building high-speed ASICs from specification to netlist, with opportunities to explore design, verification, or timing closure.

You will develop RTL in SystemVerilog, verify functionality, and partner with PD to ensure timing targets are met, while leveraging cutting-edge EDA tools and a culture that values innovation and collaboration.

Qualifications

• Bachelor’s degree in Electrical Engineering is required.
• Strong coding skills in Verilog/SystemVerilog through coursework and projects.
• Experience with RTL coding, timing closure, and PD relationships is beneficial.
• Exposure to digital logic design and computer architecture is a plus.

Responsibilities

• Start with a functional specification and develop micro-architecture for a module.
• RTL coding in SystemVerilog; work with synthesis-ready projects.
• Write functional coverage/SVA; learn to create verification environments.
• Collaborate with PD to identify timing paths and fix RTL to meet frequency targets.
• Debug blocks identified by the verification team; use state-of-the-art EDA tools for checks.

Skills

Verilog

SystemVerilog

RTL coding

Python

Perl

Analytical skills

Communication skills

Digital logic design

Education

Bachelor’s degree in Electrical Engineering

Master’s degree (preferred)

Tools

EDA tools

Job description

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.Our culture thrives onfinding new and better ways to accelerate what’s next.We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs.We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you.Open up opportunities with HPE.

Job Description:

ASIC Design Engineer 2

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Organization:

HPE is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use.At Juniper Silicon group, we push the boundaries of what is possible in a piece of silicondie. We buildcutting edgenetworking chips used to build world-class routers and switches.

Bring your passion and there are no boundaries to what you canaccomplishhere. We are likea start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips.

As part of our fast-paced chip design group, you will become an expert in building high-speed ASICs, from specifications to final netlist. Youcanpick and choosewhere you want to work on – design/ verification or timing closure/PD.As you are getting started inyourcareer, wewilllet you explore your passions here.

Open communications, empowerment, innovation,teamworkand customer success are the foundations ofteamculture.Thus, you set your own limits for learning,achievementsand rewards.

Responsibilities:

• You will start with a functional specification of a module and come up with a detailed micro-architecture specification – do not worry, you will have guidance from our senior engineers on how to go about this if you have not done this before.
• RTL coding – we prefer youknowSystem Verilog and have done severalschool/internprojects (coding to synthesis) using this language.
• Write functional coverage/SVA (we will teach you how to do this if youhaven’tdone this before)
• Timing closure –work with PD toidentifytiming paths andfix timing in RTL to meet the frequency target.
• Debug issues in your block found byverificationteam.
• Usestate-of-the-artEDA toolsfor various design checks.

Recommended skills

• Bachelor’s degree in Electrical Engineeringrequired,Master’sstronglydesired.
• Strong analytical/ problem solving skills.
• Should have taken courses for credit in digital logic design.
• Strong coding skills in Verilog/System Verilog through courses andinternprojects
• Knowledge of Computer Architecture/networking protocols/machine learning through graduate level courses is a plus.
• Excellent written and verbalcommunicationsskillsisgood to have.
• Knowledge of Perl/Pythonis a plus

We are an equal opportunity employer and value diversity at our company. We do not discriminateon the basis ofrace, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

What We Can Offer You:

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Let’s Stay Connected:

Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.

Job:

Engineering

Job Level:

TCP_02

The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
– United States of America: Annual Salary USD 105,500 - 213,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered.

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.