Architecture Design Verification CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent Inc.; Santa Clara (CA); On-site; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent Inc. is hiring a CPU Verification Fellow to lead verification strategies for high-performance RISC-V processors. The role requires deep expertise in CPU verification and microarchitecture, guiding engineering teams through various stages of processor development.

This hybrid position can be based in Santa Clara, CA or Austin, TX. Candidates will be evaluated for their experience level, with compensation ranging from $100k to $500k, tailored to individual qualifications.

Qualifications

• Deep experience in verifying high-performance superscalar CPUs.
• Strong knowledge of RISC‑V architecture and virtual memory.
• Hands-on experience with CPU reference models and ISS-based checking.

Responsibilities

• Lead verification strategy for next-generation RISC‑V processors.
• Drive verification planning for microarchitectures.
• Build and scale test plans and assertions for CPU features.

Skills

RISC‑V architecture knowledge

SystemVerilog proficiency

UVM and constrained-random verification

Out-of-order and speculative CPUs

Functional coverage expertise

Job description

CPU Verification Fellow, RISC-V High-Performance Processor

United States

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high‑performance RISC‑V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking a CPU Verification Fellow to lead verification strategy and execution for next‑generation RISC‑V high‑performance processors. This role requires deep CPU verification expertise, strong microarchitecture understanding, and the ability to guide large engineering teams from early design through tapeout and post‑silicon validation. The ideal candidate has verified complex out‑of‑order, speculative, superscalar CPUs and can define scalable methodology across simulation, formal verification, emulation, FPGA, and silicon bring‑up.

This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have deep experience verifying high-performance superscalar CPUs, ideally including out-of-order and speculative processors.
• You have strong knowledge of RISC‑V architecture, including ISA compliance, privileged architecture, virtual memory, atomics, vector extensions, and memory model behavior.
• You are highly proficient in SystemVerilog, UVM, constrained-random verification, assertions, functional coverage, and advanced debug methodologies.
• You have hands‑on experience with CPU reference models, instruction generators, ISS‑based checking, or differential testing.
• You bring practical expertise with formal verification and large‑scale CPU verification environments.

What We Need

• A verification leader who can own strategy for RISC‑V high-performance superscalar CPUs and CPU subsystems.
• An expert who can drive verification planning for out-of-order, speculative, superscalar microarchitectures.
• A technical leader who can build and scale test plans, coverage, checkers, assertions, scoreboards, and constrained‑random environments.
• Someone who can verify key CPU features including frontend, branch prediction, rename, scheduling, execution, load‑store, memory ordering, cache hierarchy, retirement, exceptions, interrupts, debug, and coherency interactions.
• A cross‑functional partner who can work closely with architecture, RTL, performance modeling, SoC, firmware, compiler, and validation teams while mentoring senior engineers and establishing best practices across the CPU verification organization.

What You Will Learn

• How Tenstorrent develops next‑generation RISC‑V high-performance superscalar processors from early design through tapeout and post‑silicon validation.
• How CPU verification strategy scales across simulation, formal verification, emulation, FPGA prototyping, and silicon bring‑up.
• How advanced CPU features such as coherency, virtual memory, atomics, vector extensions, and custom extensions are verified in complex real-world systems.
• How to drive verification closure, bug triage, root‑cause analysis, coverage closure, and tapeout readiness at the highest levels of technical leadership.
• How Tenstorrent teams collaborate across architecture, design, firmware, compiler, and validation to build cutting‑edge compute products.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.