Analog Mixed Signal IP Integration Engineer

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 150,000; Full time

Job summary

Apple Inc. is looking for an Analog Mixed Signal IP Integration Engineer in Beaverton, Oregon. The role involves supporting the integration of third-party IP in SOCs and working closely with cross-functional teams.

Minimum qualifications include a BSEE/MSEE and over 7 years of industry experience, with preferred qualifications in Verilog modeling and SOC design flow. Join us to contribute to products that delight millions.

Qualifications

• 7+ years of industry related experience.
• Experience writing Verilog, SystemVerilog, SVA.
• Deep knowledge of front-end tools.

Responsibilities

• Define and specify deliverable requirements for IP.
• Drive discussions with vendors regarding requirements.
• Support SOC front-end and back-end design teams.

Skills

Verilog modeling

RTL design

Communication Skills

SOC design flow knowledge

Education

BSEE/MSEE

Tools

Simulation tools

Synthesis tools

Static timing analysis tools

Job description

Analog Mixed Signal IP Integration Engineer

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and especially motivated Analog Mixed Signal IP Integration Engineer! As a member of our dynamic group, you will have the rare and great opportunity to work on upcoming products that will delight and encourage millions of Apple’s customers every day!

Description

In this highly visible role, you will support the integration of 3rd party IP in the SOCs developed by Apple. Your job is to verify that the IP deliverables are meeting Apple's high quality standards and get flawlessly integrated. The role involves working closely with different cross-functional teams within Apple as well as with external vendors. Occasional travel might be required.

Responsibilities

• Define and specify deliverable requirements for IP provided by external vendors
• Driving discussions with vendors regarding these requirements, their design and verification methodology
• Review IP quality on incoming deliverables
• Provide support to Apple SOC front-end and back-end design teams for integrating the IP

Minimum Qualifications

• BSEE/MSEE and 7+ years industry related experience.

Preferred Qualifications

• Experience with Verilog modeling and model validation is a plus
• Experience with standards like PCI Express, MIPI, USB or DisplayPort is a plus
• Excellent written and verbal communication skills
• Strong initiative and ownership of responsibilities, productive, able to meet aggressive deadlines
• Experience in RTL design, verification or integration
• Deep knowledge and experience with front-end tools such as simulation, synthesis, lint, logic equivalence, static timing analysis, CDC, RDC, and UPF
• Familiarity with SOC design flow and verification methodologies
• Good understanding of DFT requirements for SOCs
• Experience writing Verilog, SystemVerilog, SVA hardware description languages

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

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Apple accepts applications to this posting on an ongoing basis.