Analog IC Design Intern – Winter/Spring 2027

Skyworks Solutions, Inc; Austin (TX); On-site; USD 36,000 - 65,000; Full time

Job summary

Skyworks Solutions, Inc. is seeking an Analog Design Intern for Winter/Spring 2027 in Austin.

You will contribute to analog mixed-signal ICs for EV, AI data centers, and industrial power applications while engaging in block architecture, detailed circuit design, and layout supervision. The candidate should be a current student pursuing a Bachelor’s, MSEE or PhD in electrical engineering with familiarity in Cadence tools and CMOS behavior.

Qualifications

• Current student pursuing a Bachelor's, MSEE or PhD in electrical engineering.
• Familiarity with cadence design tools and CMOS concepts.
• Experience with opamps, regulators and references; understanding loop dynamics.

Responsibilities

• Architects, designs and verifies circuits, systems and/or algorithms to meet product requirements.
• Deliver work product in a timely manner to ensure business success.
• Demonstrates good judgment and quantitative analysis in solving design problems.
• Regularly presents design reviews to demonstrate results and obtain feedback.
• Attends design reviews to provide input and learn from other designer's experiences.
• Research design techniques through review of previous product documentation and trade publications.
• Validates a design meets all the required specifications.

Skills

Cadence tools familiarity

CMOS transistor behavior

AC/DC analysis

Opamps and references

Time/frequency analysis

CMOS layout

Lab equipment experience

Presentation skills

Education

Bachelor's/MSEE/PhD in EE

Tools

Cadence design tools

Job description

Skyworks Solutions, Inc. is seeking an Analog Design Intern for Winter/Spring 2027 in Austin.

You will contribute to analog mixed-signal ICs for EV, AI data centers, and industrial power applications while engaging in block architecture, detailed circuit design, and layout supervision. The candidate should be a current student pursuing a Bachelor’s, MSEE or PhD in electrical engineering with familiarity in Cadence tools and CMOS behavior.