Analog ASIC Engineer for Quantum Computers (Remote 2 days/wk)

Quantinuum; Broomfield (CO); Hybrid; USD 136,000 - 170,000; Full time

Benefits offered by this job

Competitive compensation

Flexible work arrangements

Medical, dental, and vision insurance

401(k) with company match

Equity opportunities

Paid time off

Paid parental leave

Employee discounts

Job summary

Quantinuum in Broomfield, Colorado is seeking an Analog ASIC Electrical Engineer to lead the development of ASIC designs for the Apollo and Lumos quantum computers. The role emphasizes analog CMOS circuit design, transistor-level design and simulation, and collaboration with fabs to integrate designs within complex electrical systems.

You will work with ASIC designers, quantum architecture and packaging teams to translate system requirements into scalable IP, addressing reliability and

Qualifications

• Bachelor’s Degree minimum.
• 5+ years IC design experience in a design/R&D environment.
• 3+ years analog ASIC design, development, verification and test.

Responsibilities

• Architect and implement ASICs for quantum computer roadmap.
• Design and optimize analog/mixed-signal ICs in advanced CMOS processes.
• Translate requirements into architectures, plans, and verification strategies.
• Collaborate with system architects, digital designers, verification and packaging teams.
• Deploy ASICs in cryogenic, ultra-high vacuum, and noise-sensitive environments.
• Co-author test plans and participate in silicon bring-up and debugging.

Skills

Analog CMOS design

Transistor-level design

Circuit simulation

High-voltage design

Fabric interaction

Education

Bachelor’s degree

Tools

EDA tools

Job description

Quantinuum in Broomfield, Colorado is seeking an Analog ASIC Electrical Engineer to lead the development of ASIC designs for the Apollo and Lumos quantum computers. The role emphasizes analog CMOS circuit design, transistor-level design and simulation, and collaboration with fabs to integrate designs within complex electrical systems.

You will work with ASIC designers, quantum architecture and packaging teams to translate system requirements into scalable IP, addressing reliability and