AMS Design Verification Engineer – Analog Mixed-Signal

Texas Instruments Incorporated; Santa Clara (CA); On-site; USD 130,000 - 170,000; Full time

Job summary

Texas Instruments Incorporated is seeking a Design Verification Engineer-AMS in Santa Clara, CA. You will define, design, and document digital cores for battery management devices, interacting with key customers to translate visions into robust verification strategies.

You will drive modelling, simulation, and environment development for mixed-signal blocks, implementing real-time and post-processing checkers, and leading full-cycle verification from RTL to tape-out within a fast-paced team.

Qualifications

• Detail-driven verification planning and coverage-driven methodology.
• Experience modelling and simulating analog/digital cores for battery management devices.
• Ability to build and maintain mixed-signal testbenches and verification environments.

Responsibilities

• Develop detailed verification plans in collaboration with System, Application, and Analog Design teams.
• Create high-fidelity analog behavioral models using Verilog-A/Verilog-AMS/Wreal for efficient top-level sims.
• Build and enhance mixed-signal testbenches combining schematic, models, and RTL.
• Implement checkers and assertions for real-time and post-processing verification.
• Perform RTL and gate-level simulations, manage regressions, and track functional coverage goals.
• Collaborate with DV, Analog, and Post-Silicon teams to debug complex issues.

Skills

Verification strategy

Testbench development

Analog/digital DV

Collaboration

RTL/GLS verification

Tools

Verilog-A

Verilog-AMS

Wreal (RNM)

Job description

Texas Instruments Incorporated is seeking a Design Verification Engineer-AMS in Santa Clara, CA. You will define, design, and document digital cores for battery management devices, interacting with key customers to translate visions into robust verification strategies.

You will drive modelling, simulation, and environment development for mixed-signal blocks, implementing real-time and post-processing checkers, and leading full-cycle verification from RTL to tape-out within a fast-paced team.