AI Systems Architect - Models & Hardware Co-Design (Hybrid)

Velaura AI, Inc.; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Velaura AI, Inc. is seeking an AI Systems Architect to bridge machine learning models and hardware design. You will shape AI workloads for next-gen compute platforms, evaluating models and translating them into efficient hardware implementations.

You will collaborate across software and hardware teams, assess training and inference characteristics, and help optimize dataflows and compute patterns for silicon realization. This role blends math, ML, and hardware expertise.

Qualifications

• Experience with modern ML model architectures, including transformers.
• Strong grounding in ML foundations, optimization, and deep learning.
• Experience using ML frameworks such as PyTorch, JAX or TensorFlow.

Responsibilities

• Analyze modern AI model architectures including transformers and other options to understand compute needs.
• Evaluate model suitability for different domains and workloads.
• Collaborate with hardware architects to translate model requirements into silicon implementations.
• Identify opportunities to modify or optimize models, algorithms, or dataflows to improve performance and efficiency on hardware.
• Understand training and inference pipelines and their implications for hardware design.
• Develop performance and efficiency models to guide architectural decisions.
• Work with software and hardware teams to deploy models on new compute platforms.
• Stay current with emerging AI model research and assess when new architectures benefit from specialized hardware.

Skills

Transformers

ML architectures

Model computation graphs

PyTorch

JAX

TensorFlow

Hardware co-design

Job description

Velaura AI, Inc. is seeking an AI Systems Architect to bridge machine learning models and hardware design. You will shape AI workloads for next-gen compute platforms, evaluating models and translating them into efficient hardware implementations.

You will collaborate across software and hardware teams, assess training and inference characteristics, and help optimize dataflows and compute patterns for silicon realization. This role blends math, ML, and hardware expertise.