AI Model Architect

Ericsson GmbH; Austin (TX); On-site; USD 150,000 - 200,000; Full time

Benefits offered by this job

Competitive salary

Health benefits

401(k) plan with matching

Paid time off and parental leave

Job summary

Ericsson GmbH in Austin, Texas is seeking a Principal AI Model Architect to revolutionize the integration of AI models with silicon hardware. In this pivotal role, you'll leverage your expertise to translate cutting-edge AI algorithms into precise hardware specifications, ensuring seamless functionality.

Candidates should possess deep knowledge of Transformer architectures, as well as proficiency in JAX and PyTorch. The position offers a comprehensive benefits package, including competitive salary, health benefits, and vacation time.

Qualifications

• Deep knowledge of Transformer architectures and design choices.
• Experience in hardware-aware machine learning.
• Advanced proficiency in JAX, PyTorch, or TensorFlow.

Responsibilities

• Translate AI algorithms into hardware specifications.
• Define strategies for model partitioning and tiling.
• Maintain canonical reference implementations in major ML frameworks.

Skills

Model Architecture Mastery

Hardware‑Aware ML

Framework Depth

Performance Modeling

Education

Advanced degree in relevant field

Tools

JAX

PyTorch

TensorFlow

SystemC

Job description

Grow with us

AI Model Architect — Silicon-Software Co-Design

Austin, Texas

The Voice of the Model. The Architect of the Machine.

The Mission

Most AI architects optimize models for hardware that already exists. You're going to shape the hardware around the model — before a single transistor is placed.

As our Principal AI Model Architect, you occupy the most strategically critical seat in our entire silicon program. You are the living contract between what our researchers dream up and what our silicon team can physically build. You are the person in the room who looks at a state‑of‑the‑art Transformer architecture and answers the question no one else can:

"Here’s exactly how we break this apart, map it across our heterogeneous ASIC, and run it faster than anyone else on earth — and here's the proof."

This isn't model fine‑tuning. This isn't prompt engineering. This is deep, architecture-level surgery — partitioning massive-parameter models, defining tiling strategies, projecting cycle‑accurate performance on silicon that doesn't exist yet, and ensuring the SDK team has a mathematically airtight path to make it all real.

Your decisions don't just influence software. They get etched into silicon.

What You'll Actually Be Doing

Hardware‑Software Bridge — Own the Translation Layer

You’ll take bleeding‑edge AI and RAN algorithms — Transformers, Grouped Query Attention, Rotary Positional Embeddings — and convert them into precise hardware specifications for the ASIC team and concrete lowering requirements for the SDK team. You're not summarizing research. You're operationalizing it, making it real at the level of memory hierarchies, dataflow patterns, and execution units.

Model Partitioning & Tiling — Shatter the Model

You’ll define the strategies for how massive, multi‑hundred‑million parameter models get decomposed and mapped across heterogeneous compute fabrics. Tensor parallelism, pipeline stages, tiling across HBM and on‑chip SRAM — you architect the playbook that determines how every layer lives and breathes on custom silicon.

Golden Model Ownership — Guard the Source of Truth

You’ll own and maintain the canonical reference implementations in JAX and PyTorch — the undisputed “Source of Truth” that the entire program aligns to. When the MLIR‑compiled output lands on silicon, it’s your models that prove whether the math held. You’ll work hand‑in‑hand with the SDK team to ensure that what the researcher intended and what the hardware executes are identical, bit for bit.

Performance Projection — See the Future in Cycles

Before a single line of RTL is written, you’ll be projecting performance. Using cycle‑accurate simulators, SystemC models, and your own deep intuition for how model architectures behave under hardware constraints, you’ll give the silicon team the confidence to make tape‑out decisions that cost millions of dollars. You are the signal in the noise.

What You Bring

• Model Architecture Mastery – You have deep, battle‑tested knowledge of Transformer architectures — not just how they work conceptually, but how every design choice (attention head count, KV‑cache sizing, embedding strategies, GQA vs. MQA trade‑offs) ripples through a hardware execution profile.
• Hardware‑Aware ML — The Rare Skill – You’ve lived in the “Hardware‑in‑the‑Loop” world. You think about cache line behavior, memory wall bottlenecks between HBM and SRAM, and how SIMD and VLIW execution units reward or punish specific model shapes. You don’t just write models — you profile them against physics.
• Framework Depth — Down to the Graph – Advanced proficiency in JAX (strongly preferred), PyTorch, or TensorFlow – specifically at the export and compilation layer. You’re comfortable with graph capture, XLA compilation, and StableHLO representations. You know what happens to your model after the Python interpreter is done with it.
• Performance Modeling – Experience with SystemC, Transaction‑Level Modeling, or custom cycle‑accurate simulation frameworks. You’ve used these tools to validate architectural decisions before silicon is committed — and you’ve been right when it counted.

Preferred Expertise — The Gap‑Fillers That Set You Apart

• Telecommunications DNA – You’ve applied AI to real RAN workloads – channel estimation, beamforming, interference management at L1/L2/L3. You understand why 5G inference isn’t just a data‑center problem in a smaller box.
• Compiler Curiosity – You don’t need to write MLIR transformation passes from scratch – but you instinctively understand the journey from a high‑level compute graph to a linearized, scheduled, hardware‑bound execution sequence. You know what gets lost in that translation and how to protect against it.
• Numeric Sensitivity – You have hands‑on experience with complex‑valued AI models and the specific challenges they create when mapping to DSP and matrix accelerator hardware. Fixed‑point quantization, dynamic range, numerical stability under precision reduction – these aren’t abstract concerns to you. They’re design constraints.

Why This Role Is Different

There are thousands of ML engineers who can train a Transformer. There are hundreds who can write a compiler pass. There are dozens who can design an ASIC datapath.

This is THE role. If you’ve spent your career sitting at the uncomfortable, exhilarating intersection of research and silicon – and you’re ready to do the most consequential work of your career – we want to talk.

What happens once you apply?

Click Here to find all you need to know about what our typical hiring process looks like.

Equal Opportunity Employer

Ericsson uses a merit‑based hiring approach that values people with different experiences, perspectives and skillsets. We truly believe this approach drives innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity employer, learn more.

If you need assistance or to request an accommodation due to a disability, please contact Ericsson at [e-mail].

DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.

Job Details

Primary country and city: USA || Austin, Texas

Compensation and Benefits at Ericsson

At Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.

Your Pay

The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job‑related knowledge, qualifications, skills, education, training, and experience.

Your Health

Ericsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.

Your Financial Security

We invest in both your short and long‑term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson’s full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short‑term and long‑term disability coverage. Employees also have the option to participate in Ericsson’s Stock Purchase Plan.

Your Time

Your work‑life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro‑rated based on the employee’s start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.

Additional Benefits

Ericsson offers many other company‑paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.