AI/ML ASIC Architect

SanDisk; California; On-site; USD 180,000 - 320,000; Full time

Job summary

Sandisk is seeking an AI/ML ASIC Architect to develop architectures for AI Storage Solutions and accelerators. You will drive frontend architecture, collaborate across RTL/DV/FW and product planning, and push innovations for high-performance, power-conscious datacenter solutions.

You will work with cross-functional teams to define SoC requirements, assess PPA tradeoffs, and guide pre/post-silicon validation efforts while shaping the roadmap for next-generation AI storage accelerators.

Qualifications

• Bachelor's/Master's/PhD in Computer/Electrical Engineering with 15+ years of hands-on architecture experience.

Responsibilities

• Drive AI/ML ASIC architecture for AI Storage with accelerators over UCIe/PCIe/CXL.
• Author architecture specifications for AI/ML xPU-based accelerators.
• Define I/O subsystem and PCIe DMA architectures and interactions with subsystems.
• Create modular I/O subsystem architectures for Chiplet/monolithic/3D form factors.
• Scope SoC requirements with customers and cross-functional teams to meet PPA/schedule targets.
• Define DMA hardware/software/firmware interfaces with embedded subsystems and CPUs.
• Guide pre-silicon design/verification and post-silicon validation.
• Improve AI/ML ASIC performance via hardware/software co-optimization and roadmap influence.
• LLM workload analysis to identify performance opportunities in products.
• Experience architecting components like HBM, PCIe/UCIe/CXL, NoC, DMA, Firmware interactions, NAND, xPU.

Job description

**Company Description**

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

**Job Description**

In this AI/ML ASIC Architecture position, you will develop AI Storage Solutions based advanced system architectures and AI/ML Accelerator ASIC architecture specifications for Sandisk's next generation products. You will drive, initiate, and analyze frontend architecture of the AI/ML Accelerator product. As an AI/ML ASIC Architect you will help drive new architecture initiatives that leverage the state-of-the‑art frontend interfaces like UCIe, PCIe, CXL, etc that integrates AI Storage Solutions with xPU in a 3D package system. You will drive the AI Storage Solutions based architecture. You will exercise your technical expertise and excellent communication skills to collaborate with design and product planning with an eye towards delivering innovative and highly competitive adaptive accelerators solutions. Typical activities include writing architecture spec, working with other architects in the team, work with RTL/DV/Simulation/Emulation/FW teams to evaluate these changes and assess the performance, power, area, and endurance of the product. You will work closely with excellent colleague engineers, cope with complex challenges, innovate, and develop products that will change the data centric architecture paradigm.

**Essential Duties and Responsibilities**

• Responsible for driving the AI/ML ASIC architecture that integrates the AI Storage with GPU/TPU/xPU accelerators, with a particular focus on I/O subsystems connected over UCIe/ PCIe/CXL


• Author architecture specifications in clear and concise language for AI/ML xPU based Accelerator using AI Storage Solutions.


• Define I/O subsystem and PCIe DMA architectures, including their interactions with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric.


• Create flexible and modular I/O subsystem architectures that can be deployed in either Chiplet, monolithic or 3D form factors.


• Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets.


• Define SoC subsystem and DMA hardware, software, and firmware interactions with embedded processing subsystems and SoC CPUs on the device side and Host CPUs.


• Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase.


• Responsible for improving the AI/ML ASIC Architecture performance through hardware & software co-optimization, post-silicon performance analysis, and influencing the strategic product roadmap.


• Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets.


• Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase.


• LLM Workload analysis and characterization of ASIC and competitive datacenter and AI solutions to identify opportunities for performance improvement in our products.


• Experience architecting one or some components of AI/ML accelerator ASICs such as HBM, PCIe/UCIe/CXL, NoC, DMA, Firmware Interactions, NAND, xPU, fabrics, etc


• Drive the AI Storage Solutions frontend system architecture with GPU/TPU/NPU/xPU to match or exceed the nextgen HBM bandwidth


• Architect memory-efficient inference/training systems utilizing techniques like pruning, quantization with MX format , continuous batching/chunked prefill, and speculative decoding


• Collaborate with internal and external stakeholders/ML researchers to disseminate results and iterate at rapid pace

**Qualifications**

**Required:**

• Bachelors or Masters or PhD in Computer/Electrical Engineering with 15+ years of hands‑on Architecture experience authoring s