Agentic AI Chip Design Engineer (Hybrid) — Equity

NVIDIA Gruppe; Santa Clara (CA); Hybrid; USD 224,000 - 356,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Gruppe in Santa Clara, CA is seeking an experienced engineer to advance ASIC design with agentic AI. You will apply LLMs and coding agents to core design problems, moving faster than traditional workflows and delivering results end-to-end.

The role requires 8+ years in front-end ASIC design, hands-on AI tooling, and a track record of taking ideas from conception to production. Hybrid work and equity benefits are available.

Qualifications

• MS or PhD or equivalent experience in CS/EE.
• 8+ years of industry experience.
• Expertise in front-end ASIC design, verification, timing.
• Hands-on with LLM-based agents and AI tooling.
• Experience with custom model training and post-training.
• Excellent self-motivation, collaboration, and communication.
• Infrastructure experience (Docker, Slurm, CI/CD).
• Strong written and verbal communication.

Responsibilities

• Apply LLMs, coding agents, and agentic systems to ASIC design problems.
• Hands-on experience with LLMs, RL, RLHF/RLAIF, post-training, evaluation, graders, synthetic data.
• Deliver against internal chip design schedules, accelerating ASIC teams.
• Build robust data generation and evaluation methodology to discriminate production from demos.
• Wire coding agents into EDA and validation flows to drive complex tasks.
• Push limits with models on open-source foundations and iterate to production.
• Partner with Nemotron team to improve models with domain-specific data.

Skills

Front-end ASIC design

Agentic AI in design

LLM-based agents

Tool integration

Evaluation focused

Model fine-tuning

CI/CD tooling

Communication skills

Education

MS or PhD in CS/EE

Tools

Docker

Slurm

CI/CD pipelines

Job description

NVIDIA Gruppe in Santa Clara, CA is seeking an experienced engineer to advance ASIC design with agentic AI. You will apply LLMs and coding agents to core design problems, moving faster than traditional workflows and delivering results end-to-end.

The role requires 8+ years in front-end ASIC design, hands-on AI tooling, and a track record of taking ideas from conception to production. Hybrid work and equity benefits are available.