Advanced Packaging SI/PI Engineer

Etched; San Jose (CA); On-site; USD 130,000 - 160,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

Housing subsidy of $2k per month

Relocation support to San Jose

Daily lunch and dinner in office

Job summary

Etched in San Jose seeks a Signal & Power Integrity Engineer to ensure top electrical performance of its AI accelerator platform. The ideal candidate will drive signal and power integrity analysis, collaborate with design teams, and optimize layouts for high-performance ASICs. A Bachelor’s or Master’s in Electrical Engineering and 8+ years of experience in SI/PI are required. The company offers a relocation subsidy, daily meals, and health benefits including generous premium coverage.

Qualifications

• 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms.
• Hands-on expertise with one or more relevant simulation tools.
• Strong analytical and communication skills to present risks and trade-offs.

Responsibilities

• Conduct SI/PI analysis of designs and optimize electrical performance.
• Drive SI requirements into interposer/substrate layout and own pin assignments.
• Participate in cross-functional meetings and design reviews.

Skills

Signal Integrity analysis

Power Integrity design

Communication skills

Creativity

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related

Tools

ANSYS HFSS

Cadence Sigrity

Keysight ADS

Job description

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real‑time video generation models and extremely deep & parallel chain‑of‑thought reasoning agents. Backed by hundreds of millions from top‑tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a Signal & Power Integrity Engineer you will be responsible for the electrical performance of our AI accelerator platform across silicon, package, and board. The ideal candidate will have extensive experience with high‑power package and board designs, robust power delivery networks, and high‑speed signaling solutions in advanced packaging. You will work closely with silicon, package, platform, and system teams to co‑design world‑class platforms with OSAT and ODM partners. Intense focus on pushing what is possible in power delivery and high‑speed signaling for transformer‑purposed silicon.

Key Responsibilities

• SI/PI analysis of designs and optimization within 2D/2.5D/3D packages
• Close interaction with Package Layout Designers, ASIC PD and IP teams as well as Board Schematic/Layout/SI/PI teams to optimize the best electrical performance
• Drive SI requirements into interposer/substrate layout (high‑speed routing: 112G/224G) from preliminary design through tape‑out.
• Drive PDN design and decoupling strategy across substrate and interposer, owning DC IR drop, dynamic IR drop, and impedance targets across all rails.
• Own ball map / C4 / BGA pin assignment from soft freeze through final freeze in partnership with package layout, ASIC PD, and board layout teams.
• Support board‑level SI/PI and rack‑level scale‑up topology studies, including rack test vehicle design and cable characterization.
• Participating in cross‑functional meetings and design reviews.

You may be a good fit if you have (Must‑have qualifications)

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field with a strong understanding of signal integrity and power integrity concepts and fundamentals.
• 8+ years of SI/PI experience on high‑performance ASIC, processor, or accelerator platforms.
• Proven experience defining and closing PDN for high‑power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis.
• Experience with developing systems with high‑speed interfaces like HBM, SerDes and D2D interfaces.
• Hands‑on expertise with one or more of: ANSYS HFSS / SIwave, Cadence Sigrity (PowerSI / PowerDC), Keysight ADS.
• Experience with CoWoS or equivalent advanced packaging materials and technologies including interposer SI/PI implications, C4 bump planning, and substrate stack‑up trade‑offs.
• Track record of designing and correlating SI/PI test vehicles against silicon measurement during bring‑up and lab characterization.
• Strong analytical and communication skills, comfortable presenting risk, sign‑off status, and trade‑offs to cross‑functional leadership.
• Deeply creative and able to think from first principles.

Strong candidates may also have experience with (Nice‑to‑have qualifications)

• Familiarity with full RTL‑to‑GDSII context and how PD decisions interact with package and board PDN.
• Experience with multi‑die, 2.5D, or 3D packaging signoff, including chip‑package‑system (CPS) co‑design.
• Project management experience coordinating across internal teams, OSAT partners, and PCB ODMs.
• Familiarity with transformer models, accelerator architectures, or HPC system design.
• Startup experience or comfort working in fast‑paced environments.

Benefits

• Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
• Housing subsidy of $2k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch and dinner in our office

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model‑specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single‑model ASICs.

We are a fully in‑person team in San Jose and Taipei, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.