3D Physical Design Engineer

Cerebras; Sunnyvale (CA); On-site; USD 150,000 - 200,000; Full time

Job summary

A pioneering AI chip company in Sunnyvale seeks a 3D Integration Design Engineer to design and analyze advanced 3D integrated designs. The role requires over 10 years of physical design experience, with expertise in verification methodologies, optimization for power and area, and proficiency in scripting languages. You will work alongside teams for R&D on novel integration concepts. This is an opportunity to contribute to the development of the world's largest AI chip technology.

Qualifications

• 10+ years of physical design/verification experience.
• Expert at optimizing for the best power/performance and area.
• Strong ability in scripting languages like Tcl and Python.

Responsibilities

• Design and analyze 3D integrated designs.
• Work closely with architecture and RDL team on R&D for 3D integration.
• Resolve block and full-chip DRC and LVS issues.

Skills

Physical design/verification experience

Block level and full-chip physical verification methodology

Power/performance and area optimization

Complete physical design flow knowledge

ICV or Calibre tools proficiency

IR/EM analysis skills

Scripting languages expertise (Tcl, Python)

Collaboration with RTL teams

2.5D or 3D packaging knowledge

Tools

Synopsys tool suite

Calibre

Job description

3D Integration Design Engineer

As a member of our tight knit physical design team, you will design and analyze 3D integrated designs. This role involves a combination of traditional ASIC/SoC physical design skills, packaging, power, clock and cooling analysis. You will work closely with the architecture and RDL team to conduct R&D on novel concepts for 3D integration.

Skills & Qualifications

Required

• 10+ years of physical design/verification experience.
• Strong knowledge of block level and full-chip physical verification methodology.
• Expert at optimizing for the best power/performance and area.
• Experience with the complete physical design flow. Knowledge of Synopsys tool suite is a plus.
• Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues.
• Expert with IR/EM analysis and resolution.
• Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements.
• Demonstrated ability to work with RTL teams to optimize for physical design.
• Knowledge of 2.5D or 3D packaging solutions.

Preferred

• Experience doing full chip floor planning and integration.
• Knowledge of clock distribution.
• Knowledge of cooling analysis.

Company Overview

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.

Cerebras' current customers include global corporations across multiple industries, national labs, and top-tier healthcare systems. In January, we announced a multi-year, multi-million-dollar partnership with Mayo Clinic, underscoring our commitment to transforming AI applications across various fields. In August, we launched Cerebras Inference, the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services.

EEO Statement

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.