Senior AI Silicon Physical Design Engineer

Cerebras; Sunnyvale (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Cerebras Systems in Sunnyvale, California, is seeking a senior Physical Design Engineer to own the full PD flow for high-speed designs, from synthesis to routing, and to integrate blocks into the die-wide architecture in collaboration with the RTL team.

You will optimize power, performance, and area, drive timing closure at block and full-chip levels, perform IR/EM analysis, and develop floorplanning strategies.

Qualifications

• 10+ years of physical design & physical verification experience.
• Strong knowledge of block level and full-chip physical verification methodology.
• Strong experience in block/subsystem timing closure.
• Expert at optimizing for the best power/performance and area.
• Experience with the complete physical design flow.
• Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues.
• Expert with IR/EM analysis and resolution.
• Strong background in STA, constraint drafting and timing convergence at block, partition and fullchip.
• Should demonstrate and raise the bar for "ownership", "deep dive" and should demonstrate strong fundamental understanding of PD concepts.
• Good understanding of full chip floor planning and integration.
• Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements.
• Demonstrated ability to work with RTL teams to optimize for physical design.
• Skills in Design Compiler, Fusion Compiler, ICC2 or similar physical design tools.
• BS or MS in Electrical Engineering.

Responsibilities

• Synthesize, place, and route high-speed designs.
• Collaborate with RTL team to optimize physical design.
• Integrate blocks into the full-chip architecture.
• Drive the complete physical design flow from synthesis to DRC/LVS resolution.

Skills

Physical design

Timing closure

Power optimization

IR/EM analysis

Scripting Tcl/Python

RTL collaboration

IR/VC tool knowledge (Calibre/ICV)

Floorplanning

Full-chip flow

Ownership & deep-diving

Education

BS or MS in Electrical Engineering

Tools

Design Compiler

Fusion Compiler

ICC2

Job description

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.

This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

About The Role

Join our close-knit physical design team where you'll excel in synthesizing, placing, and routing high speed designs. Experience the full spectrum of physical design and implementation, collaborating closely with the RTL team and integrating these blocks seamlessly into the full-chip architecture.

Skills & Qualifications

• 10+ years of physical design & physical verification experience.
• Strong knowledge of block level and full-chip physical verification methodology.
• Strong experience in block/subsystem timing closure.
• Expert at optimizing for the best power/performance and area.
• Experience with the complete physical design flow.
• Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues.
• Expert with IR/EM analysis and resolution.
• Strong background in STA, constraint drafting and timing convergence at block, partition and fullchip.
• Should demonstrate and raise the bar for “ownership”, “deep dive” and should demonstrate strong fundamental understanding of PD concepts.
• Good understanding of full chip floor planning and integration.
• Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements.
• Demonstrated ability to work with RTL teams to optimize for physical design.
• Skills in Design Compiler, Fusion Compiler, ICC2 or similar physical design tools.
• BS or MS in Electrical Engineering.
  
  

Preferred

• Knowledge of CPU/GPU design a plus.
• Block/partition PD, PDV, IR would be good to have.
• Knowledge of Synopsys tool suite is a plus.
  
  

The salary range for this position is $150,000 – $250,000 annually. Actual compensation will be determined based on factors such as experience, skills, qualifications, and location.

Why Join Cerebras

About

People who are serious about software make their own hardware. At Cerebras, we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:

• Build a breakthrough AI platform beyond the constraints of the GPU.
• Publish and open source their cutting-edge AI research.
• Work on one of the fastest AI supercomputers in the world.
• Enjoy job stability with startup vitality.
• Our simple, non-corporate work culture that respects individual beliefs.
  
  

Find out more about what it's like to work at Cerebras here!

Apply today and become part of the forefront of groundbreaking advancements in AI!

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

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