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Standard Cell Library Design Engineer

Broadcom

Northwest

On-site

SGD 60,000 - 100,000

Full time

11 days ago

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Job summary

Join a forward-thinking company that specializes in cutting-edge silicon technologies. As a key member of the Central Engineering Group, you will play a vital role in designing and developing standard cell library foundation IP. This position offers the opportunity to work with advanced circuit design techniques and collaborate with talented engineers. Your expertise in digital and mixed-signal circuit design, along with proficiency in industry-standard EDA tools, will contribute to the innovation of leading silicon products. If you are passionate about technology and eager to make an impact, this role is perfect for you.

Qualifications

  • 2+ years of experience in digital or mixed-signal circuit design.
  • Strong understanding of EDA tools and cell layout.

Responsibilities

  • Design standard cells at the transistor level.
  • Simulate and analyze circuit designs.

Skills

Digital circuit design
Mixed-signal circuit design
Verilog
EDA tools
Scripting (Unix, Perl, TCL, Python)

Education

Bachelor's in Electrical Engineering
Master's or PhD in related field

Tools

Virtuoso
Cadence Skill programming

Job description

Job Description

Broadcom's Central Engineering Group builds the Foundation IP that powers Broadcom's leading silicon product families.

In this position, the successful candidate will be part of the team responsible for the design, development, and delivery of standard cell library foundation IP.

Job Responsibilities
  1. Design standard cells at the transistor level
  2. Simulate and analyze circuit designs
  3. Generate and verify library EDA models
  4. Run regression and other quality checks on library deliverables
  5. Interface with design teams to support their requirements
Key Requirements
  • Digital or mixed-signal circuit design knowledge
  • Understanding of cell layout or physical design
  • Understanding of FinFET, RibbonFET/GAA process nodes
  • Understanding of Verilog, LEF, .lib, and other industry-standard EDA models
  • Familiarity with EDA tools used in STA and PnR
  • Experience with .lib syntax including NLDM/CCS/LVF is a plus
  • Experience with Virtuoso, Cadence Skill programming, scripting using Unix, Perl, TCL, or Python is strongly desired
Qualifications & Experience

Bachelor's in Electrical or Computer Engineering with 2+ years of related experience required. Candidates with a Master's or PhD are preferred. Singapore Citizens/PRs only.

Additional Qualifications
  • Excellent written and verbal communication skills
  • Ability to collaborate and work within and across teams
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