Staff / Senior R&D Engineer - Wafer Bumping (Up $10000 + AWS + VB, Northeast)

RecruitFirst Pte. Ltd; Singapore; On-site; SGD 80,000 - 100,000; Full time

Job summary

A leading company in the semiconductor industry is seeking a Technical Project Leader to drive innovation in wafer-level packaging and advanced bumping technologies. The role focuses on process development, collaboration with cross-functional teams, and optimizing yield. Successful candidates will have hands-on experience and strong knowledge of bumping technologies.

Qualifications

• 3+ years in wafer-level packaging (WLP), bumping, or advanced interconnect technologies.
• Hands-on experience with electroplating, photolithography.
• Familiarity with industry standards (JEDEC, ITRS) and simulation tools is a plus.

Responsibilities

• Oversee new product development for Wafer Bumping.
• Drive process development and optimize yield.
• Investigate bumping-related defects using analytical tools.

Skills

Solder bump/Cu pillar processes

Data analysis

Electroplating

Metrology tools

Reliability testing

Education

Bachelor's degree in relevant field

Tools

SEM

X-ray inspection

COMSOL

ANSYS

JMP

Python

SQL

Job description

Up to $10000 + AWS + VB

Semiconductor Giant

North-East SG

Job Descriptions

• Technical project leader (with cross functional team), overseeing new product development for Wafer Bumping

• Lead and innovate in advanced bumping technologies (e.g., solder, copper pillar, micro-bumps) for next-generation semiconductor packaging

• Drive process development, optimize yield, and collaborate with cross-functional teams to enable cutting-edge solutions for high-performance ICs

• Characterize and improve bump morphology, uniformity, and reliability (EM, TM, etc.).

• Develop DOE (Design of Experiments) to enhance process yield and performance

• Evaluate new bumping materials (Pb-free solders, Cu pillars, low-alpha solders) for improved electrical/thermal performance.

• Investigate bumping-related defects (voiding, cracking, misalignment) using SEM, EDX, X-ray, and other analytical tools.

Requirements

• 3+ years in wafer-level packaging (WLP), bumping, or advanced interconnect technologies.

• Hands-on experience with electroplating, photolithography, reflow, and metrology tools.

• Familiarity with industry standards (JEDEC, ITRS) and simulation tools (COMSOL, ANSYS) is a plus.

• Strong knowledge of solder bump/Cu pillar processes, UBM, and underfill materials.

• Proficiency in SEM, FIB, X-ray inspection, and reliability testing.

• Data analysis skills (JMP, Python, SQL).

*To apply, send your CV/Resume to josephyap[at]recruitfirst.com.sg with reason(s) for leaving past employments, last drawn and expected salary.

All applications will be treated with strictest confidentiality. We regret that only shortlisted candidates will be notified. Thank you.

RecruitFirst Pte Ltd E.A. 13C6342

Joseph Yap Shi Hao (R1767577)